// H:\PUBLIC_HTML\MY_PROJECTS\XDSP\61I_CORGEN_EXAMPLES_TEMP\51I\51I_ASYNC_FIFO_V4_0_VER_ISE
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Thu Nov 13 13:48:38 2003
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

`define CTLR_READ_DATA	10
`define CTLR_REFRESH	2
`define N	5
`define FWIDTH	32
`define ENABLE_MSB	3
`define C_REFRSH	1
`define SHIFT_REG_DEPTH	24
`define C_P_CHRG	2
`define FCWIDTH	2
`define C_NOP	7
`define F_DEASSERT	4
`define C_L_MODE	0
`define CTLR_LOAD_MR	4
`define WAIT_ADDRESS_3	4
`define FDEPTH	4
`define td	1
`define SYS_LOAD_MR	2
`define Q	25
`define DDR_ADDR_MSB	11
`define CTLR_ACT	5
`define DDR_ACT	3
`define WAIT_ADDRESS_0	7
`define DDR_BURST_STOP	6
`define SYS_REFRESH	6
`define OD	4
`define SYS_PRECHARGE	5
`define SYS_BURST_STOP	7
`define U_ADDR_MSB	21
`define s1	1
`define IF0	1
`define D	10
`define RES	5
`define DDR_PRECHARGE	2
`define DDR_READA	5
`define SYS_READ	3
`define CTLR_READ	7
`define COL_ADDR_MSB	7
`define DDR_WRITEA	4
`define C_READ	5
`define state_delay	6
`define DDR_NOP	7
`define T_RCD	2
`define DDR_LOAD_MR	0
`define ROW_ADDR_MSB	11
`define BR0	0
`define WAIT_ADDRESS_5	2
`define s2	2
`define s3	3
`define U_DATA_MSB	31
`define CTLR_WRITE_DATA	11
`define WAIT_ADDRESS_7	0
`define CTLR_READ_WAIT	9
`define SYS_NOP	1
`define WAIT_ADDRESS_1	6
`define C_ACTIVE	3
`define CTLR_WRITE	8
`define WAIT_ADDRESS_4	3
`define SYS_ADDR_MSB	21
`define WAIT_ADDRESS_6	1
`define IF1	2
`define s0	0
`define TCKO	0
`define DDR_DATA_MSB	15
`define CTLR_ACT_WAIT	6
`define CTLR_IDLE	1
`define F_ASSERT	2
`define IF2	3
`define WAIT_ADDRESS_2	5
`define CTLR_PRECHARGE	3
`define C_WRITE	4
`define SYS_DATA_MSB	31
`define DDR_AUTO_REFRESH	1
`define F_IDLE	1
`define s4	4
`define SYS_WRITE	4
`define C_READ_MIF	1

module design_top_tb;
	reg [15:0] din;
	reg wr_en;
	reg wr_clk;
	reg rd_en;
	reg rd_clk;
	reg ainit;
	wire [15:0] dout;
	wire full;
	wire empty;
	wire almost_full;
	wire almost_empty;
	wire [1:0] wr_count;
	wire [1:0] rd_count;
	wire rd_ack;
	wire rd_err;
	wire wr_ack;
	wire wr_err;

	design_top UUT (
		.din(din),
		.wr_en(wr_en),
		.wr_clk(wr_clk),
		.rd_en(rd_en),
		.rd_clk(rd_clk),
		.ainit(ainit),
		.dout(dout),
		.full(full),
		.empty(empty),
		.almost_full(almost_full),
		.almost_empty(almost_empty),
		.wr_count(wr_count),
		.rd_count(rd_count),
		.rd_ack(rd_ack),
		.rd_err(rd_err),
		.wr_ack(wr_ack),
		.wr_err(wr_err)
	);

	integer TX_FILE;
	integer TX_ERROR;

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	din = 16'b0000000000000000; //0
	wr_en = 1'b0;
	wr_clk = 1'b1;
	rd_en = 1'b0;
	rd_clk = 1'b1;
	ainit = 1'b1;
	// --------------------
	#100 // Time=100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=200 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=600 ns
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=700 ns
	rd_clk = 1'b0;
	ainit = 1'b0;
	// --------------------
	#100 // Time=800 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=1000 ns
	din = 16'b0000000000001110; //E
	wr_en = 1'b1;
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=1100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=1200 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	ainit = 1'b0;
	// --------------------
	#100 // Time=1300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=1400 ns
	din = 16'b0000000000001101; //D
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=1500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=1600 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=1700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=1800 ns
	din = 16'b0000000000001100; //C
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=1900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=2000 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=2100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=2200 ns
	din = 16'b0000000000001011; //B
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=2300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=2400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=2500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=2600 ns
	din = 16'b0000000000001010; //A
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=2700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=2800 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=2900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=3000 ns
	din = 16'b0000000000001001; //9
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=3100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=3200 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=3300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=3400 ns
	din = 16'b0000000000001000; //8
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=3500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=3600 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=3700 ns
	rd_clk = 1'b0;
	ainit = 1'b0;
	// --------------------
	#100 // Time=3800 ns
	din = 16'b0000000000000111; //7
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=3900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=4000 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=4100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=4200 ns
	din = 16'b0000000000000110; //6
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=4300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=4400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=4500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=4600 ns
	din = 16'b0000000000000101; //5
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=4700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=4800 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=4900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=5000 ns
	din = 16'b0000000000000100; //4
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=5100 ns
	rd_clk = 1'b0;
	ainit = 1'b0;
	// --------------------
	#100 // Time=5200 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=5300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=5400 ns
	din = 16'b0000000000000011; //3
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=5500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=5600 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=5700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=5800 ns
	din = 16'b0000000000000010; //2
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=5900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=6000 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=6100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=6200 ns
	din = 16'b0000000000000001; //1
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=6300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=6400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=6500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=6600 ns
	din = 16'b0000000000000000; //0
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=6700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=6800 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	ainit = 1'b0;
	// --------------------
	#100 // Time=6900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=7000 ns
	din = 16'b0000000000000011; //3
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=7100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=7200 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=7300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=7400 ns
	din = 16'b0000000000000110; //6
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=7500 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=7600 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=7700 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=7800 ns
	din = 16'b0000000000001001; //9
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=7900 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=8000 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=8100 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=8200 ns
	wr_en = 1'b0;
	wr_clk = 1'b0;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=8300 ns
	rd_clk = 1'b0;
	// --------------------
	#100 // Time=8400 ns
	wr_clk = 1'b1;
	rd_clk = 1'b1;
	// --------------------
	#100 // Time=8500 ns