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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
my_async_fifo YourInstanceName (
	.din(din),
	.wr_en(wr_en),
	.wr_clk(wr_clk),
	.rd_en(rd_en),
	.rd_clk(rd_clk),
	.ainit(ainit),
	.dout(dout),
	.full(full),
	.empty(empty),
	.almost_full(almost_full),
	.almost_empty(almost_empty),
	.wr_count(wr_count),
	.rd_count(rd_count),
	.rd_ack(rd_ack),
	.rd_err(rd_err),
	.wr_ack(wr_ack),
	.wr_err(wr_err));

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file my_async_fifo.v when simulating
// the core, my_async_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".