?? sin_gen.flow.rpt
字號:
Flow report for sin_gen
Fri Feb 02 15:02:25 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-----------------------------------------------+
; Flow Status ; Successful - Fri Feb 02 15:02:24 2007 ;
; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name ; sin_gen ;
; Top-level Entity Name ; sin_gen ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Met timing requirements ; No ;
; Total logic elements ; 506 / 33,216 ( 2 % ) ;
; Total registers ; 354 ;
; Total pins ; 34 / 475 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 2,048 / 483,840 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+-----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/02/2007 15:01:26 ;
; Main task ; Compilation ;
; Revision Name ; sin_gen ;
+-------------------+---------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------+-------------------------------------------------------------+---------------+-------------+------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------+-------------------------------------------------------------+---------------+-------------+------------------+
; AUTO_ENABLE_SMART_COMPILE ; On ; -- ; -- ; -- ;
; ENABLE_SIGNALTAP ; On ; -- ; -- ; -- ;
; SLD_NODE_CREATOR_ID ; 110 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_ENTITY_NAME ; sld_signaltap ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_DATA_BITS=8 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_BITS=8 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_INFO=536899072 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_POWER_UP_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK=0000000000000000000000000000000000000000 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK_LENGTH=40 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_CRC_HIWORD=53017 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_DATA_BIT_CNTR_BITS=3 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SAMPLE_DEPTH=128 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_MEM_ADDRESS_BITS=7 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_IN_ENABLED=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ADVANCED_TRIGGER_ENTITY=basic,1, ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL_PIPELINE=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ENABLE_ADVANCED_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_CRC_LOWORD=19781 ; -- ; -- ; auto_signaltap_0 ;
; USE_SIGNALTAP_FILE ; sin_gen.stp ; -- ; -- ; -- ;
+-------------------------------+-------------------------------------------------------------+---------------+-------------+------------------+
+-------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+
; Module Name ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:15 ;
; Fitter ; 00:00:21 ;
; Assembler ; 00:00:16 ;
; Timing Analyzer ; 00:00:02 ;
; Total ; 00:00:54 ;
+----------------------+--------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off sin_gen -c sin_gen
quartus_fit --read_settings_files=off --write_settings_files=off sin_gen -c sin_gen
quartus_asm --read_settings_files=off --write_settings_files=off sin_gen -c sin_gen
quartus_tan --read_settings_files=off --write_settings_files=off sin_gen -c sin_gen --timing_analysis_only
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