Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                                    ; From                                                                                                                                     ; To                                                                                                                                       ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 6.163 ns                                       ; RST                                                                                                                                      ; clk_50M_2_1Hz:inst1|lpm_counter:lpm_counter_component|cntr_f8k:auto_generated|safe_q[4]                                                  ; --                           ; CLOCK_50                     ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 21.159 ns                                      ; data_rom:inst|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|altsyncram_k7f2:altsyncram1|ram_block3a0~porta_address_reg5 ; HEX1[0]                                                                                                                                  ; CLOCK_50                     ; --                           ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 5.541 ns                                       ; CLOCK_50                                                                                                                                 ; VGA_CLK                                                                                                                                  ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 1.664 ns                                       ; altera_internal_jtag                                                                                                                     ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]                                                                                              ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 153.70 MHz ( period = 6.506 ns )               ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]                                                                  ; sld_hub:sld_hub_inst|hub_tdo                                                                                                             ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLOCK_50'                     ; N/A                                      ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; addr_gen:inst3|lpm_counter:lpm_counter_component|cntr_qkh:auto_generated|safe_q[2]                                                       ; data_rom:inst|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|altsyncram_k7f2:altsyncram1|ram_block3a0~porta_address_reg2 ; CLOCK_50                     ; CLOCK_50                     ; 0            ;
; Clock Hold: 'CLOCK_50'                      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; addr_gen:inst3|lpm_counter:lpm_counter_component|cntr_qkh:auto_generated|safe_q[0]                                                       ; data_rom:inst|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|altsyncram_k7f2:altsyncram1|ram_block3a0~porta_address_reg0 ; CLOCK_50                     ; CLOCK_50                     ; 27           ;
; Total number of failed paths                ;                                          ;               ;                                                ;                                                                                                                                          ;                                                                                                                                          ;                              ;                              ; 27           ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;