Analysis & Synthesis report for sin_gen
Fri Feb 02 15:01:40 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for data_rom:inst|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|altsyncram_k7f2:altsyncram1
 12. Source assignments for data_rom:inst|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
 13. Source assignments for data_rom:inst6|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|altsyncram_k7f2:altsyncram1
 14. Source assignments for data_rom:inst6|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
 15. Source assignments for sld_signaltap:auto_signaltap_0
 16. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_doi2:auto_generated
 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 18. Source assignments for sld_hub:sld_hub_inst
 19. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 20. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 21. Parameter Settings for User Entity Instance: data_rom:inst|altsyncram:altsyncram_component
 22. Parameter Settings for User Entity Instance: data_rom:inst|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|sld_mod_ram_rom:mgl_prim2
 23. Parameter Settings for User Entity Instance: clk_50M_2_1Hz:inst1|lpm_counter:lpm_counter_component
 24. Parameter Settings for User Entity Instance: addr_gen:inst3|lpm_counter:lpm_counter_component
 25. Parameter Settings for User Entity Instance: data_rom:inst6|altsyncram:altsyncram_component
 26. Parameter Settings for User Entity Instance: data_rom:inst6|altsyncram:altsyncram_component|altsyncram_2j91:auto_generated|sld_mod_ram_rom:mgl_prim2
 27. Parameter Settings for User Entity Instance: addr_gen:inst7|lpm_counter:lpm_counter_component
 28. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 29. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 30. SignalTap II Logic Analyzer Settings
 31. In-System Memory Content Editor Settings
 32. Analysis & Synthesis Messages



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; Legal Notice ;
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Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



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; Analysis & Synthesis Summary                                                       ;