LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  plj32 IS
port(
     clk1hz:in std_logic;
     uclk:in std_logic;
     led0:out std_logic_vector(3 downto 0);
     led1:out std_logic_vector(3 downto 0);
     led2:out std_logic_vector(3 downto 0);
     led3:out std_logic_vector(3 downto 0);
     p_cnt_en:out std_logic;
     p_rst_cnt:out std_logic;
     p_load:out std_logic
    );
end cymometer;
architecture behv of cymometer is
component cnt10
port(
     clk:in std_logic;
     rst:in std_logic;
     ena:in std_logic;
     outy:out std_logic_vector(3 downto 0);
     cout:out std_logic
    );
end component;

component reg4b
    port(
         load:in std_logic;
         din:in std_logic_vector(3 downto 0);
         dout:out std_logic_vector(3 downto 0)
        );
end component;

component testctl
    port(
          clkk:in std_logic;
          cnt_en:out std_logic;
          rst_cnt:out std_logic;
          load:out std_logic
         );
end component;

signal cnt_en:std_logic;
signal rst_cnt:std_logic;
signal load:std_logic;
signal dout0,dout1,dout2,dout3:std_logic_vector(3 downto 0);
signal cout0,cout1,cout2,cout3:std_logic;
begin
   p_cnt_en<=cnt_en;
   p_rst_cnt<=rst_cnt;
   p_load<=load;
u_testctl:testctl port map(
   clkk=>clk1hz,
   cnt_en=>cnt_en,
   rst_cnt=>rst_cnt,
   load=>load
);
u_cnt10_0:cnt10 port map(
   clk=>uclk,
   rst=>rst_cnt,
   ena=>cnt_en,
   outy=>dout0,
   cout=>cout0
);
u_cnt10_1:cnt10 port map(
   clk=>cout0,
   rst=>rst_cnt,
   ena=>cnt_en,
   outy=>dout1,
   cout=>cout1
);
u_cnt10_2:cnt10 port map(
   clk=>cout1,
   rst=>rst_cnt,
   ena=>cnt_en,
   outy=>dout2,
   cout=>cout2
);
u_cnt10_3:cnt10 port map(
   clk=>cout2,
   rst=>rst_cnt,
   ena=>cnt_en,
   outy=>dout3,
   cout=>cout3
);

u_reg4b_0:reg4b port map(
   load=>load,
   din=>dout0,
   dout=>led0
);
u_reg4b_1:reg4b port map(
   load=>load,
   din=>dout1,
   dout=>led1
);
u_reg4b_2:reg4b port map(
   load=>load,
   din=>dout2,
   dout=>led2
);
u_reg4b_3:reg4b port map(
   load=>load,
   din=>dout3,
   dout=>led3
);
end behv;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY testctl IS
PORT(
      clkk:IN STD_LOGIC;
      cnt_en:OUT STD_LOGIC;
      rst_cnt:out std_logic;
      load:out std_logic
);
END testctl;

ARCHITECTURE behv OF testctl IS
     Signal div2clk:std_logic;
Begin
Process(clkk)
Begin
if clkk'event and clkk='1'then
     div2clk<=not div2clk;
end if;
end process;
process(clkk,div2clk)
begin
   if clkk='0'and div2clk='0'then
       rst_cnt<='1';
   else
      rst_cnt<='0';
   end if;
   load<=not div2clk;
   cnt_en<=div2clk;
end process;
end behv;
--CNT10.VHD程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt10 IS 
port(
clk:in std_logic;
rst: in std_logic;
ena: in std_logic;
outy:out std_logic_vector(3 downto 0);
cout:out std_logic
);
end cnt10;

ARCHITECTURE behv OF cnt10 IS 
     signal cqi:std_logic_vector(3 downto 0);
begin
process(clk,rst, ena)
begin
if rst='1'then
     cqi<="0000";
     cout<='0';
elsif clk'event and clk='1'then
if ena='1'then
   if cqi="1001"then
     cqi<="0000";
     cout<='1';
   else
     cqi<=cqi+1;
     cout<='0';
   end if;
end if;
end if;
outy<=cqi;
end process;
end behv;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY reg4b IS
PORT(
      load:in std_logic;
      din:in std_logic_vector(3 downto 0);
      dout:out std_logic_vector(3 downto 0)
);
end reg4b;

ARCHITECTURE behv OF reg4b IS
begin
process(load)
begin
if load'event and load='1'then
     dout<=din;
end if;
end process;
end behv;