--
--  File: counter.vhd
--  十進制計數器;
--  on_off:閘門信號，clr=0:清零
--  value:十進制計數值，cary:進位信號

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity counter is
	port (
		clk: in STD_LOGIC;
		clkclr: in STD_LOGIC;
		on_off: in STD_LOGIC;
		clr: in STD_LOGIC;			
		cary: out STD_LOGIC;
		value: out INTEGER range 0 to 9
	);
end counter;   


architecture rtl of counter is
signal temp:INTEGER range 0 to 9; 
begin 
	process(clk,clr,clkclr)
	begin	
		if(clr='1' or on_off='0') then  cary<='0';temp<=0;	
     	elsif rising_edge(clk) then
   		    if(on_off='1') then	
				if(temp=9) then temp<=0;cary<='1';
				else temp<=temp+1;cary<='0';
				end if;
          end if;
    end if;
		
				
	end process;
				  	
   value<=temp;	 
   
end rtl;