?? controller.vhd
字號:
--
-- File: controller.vhd
-- 控制模塊:輸入clk1為1HZ時鐘信號,reset,輸出為LED信號和倒計時值
library IEEE;
use IEEE.std_logic_1164.all;
entity controller is
port (
clk1: in STD_LOGIC;
reset: in STD_LOGIC;
RedA: out STD_LOGIC;
RedB: out STD_LOGIC;
GreenA: out STD_LOGIC;
GreenB: out STD_LOGIC;
YellowA: out STD_LOGIC;
YellowB: out STD_LOGIC;
NumA: out INTEGER range 0 to 40;
NumB: out INTEGER range 0 to 40
);
end controller;
architecture rtl of controller is
signal cntA:integer range 0 to 70; --A:main street 70s;B:slave street 60s.
signal cntB:integer range 0 to 60;
begin
process(clk1,reset)
begin
if(reset='1') then
cntA<=0;
cntB<=0;
elsif rising_edge(clk1) then
if(cntA=69) then cntA<=0;
else cntA<=cntA+1;
end if;
if(cntB=59) then cntB<=0;
else cntB<=cntB+1;
end if;
end if;
end process;
process(clk1,reset)
begin
if(reset='1') then
RedA<='0';
RedB<='0';
GreenA<='0';
GreenB<='0';
YellowA<='0';
YellowB<='0';
elsif rising_edge(clk1) then
if(cntA<20) then -- 前20s主干路紅燈亮
RedA<='1';
GreenA<='0';
YellowA<='0';
NumA<=20-cntA;
elsif(cntA<60) then --21-60s主干路綠燈亮
RedA<='0';
GreenA<='1';
YellowA<='0';
NumA<=60-cntA;
else --61-70s主干路黃燈亮
RedA<='0';
GreenA<='0';
YellowA<='1';
NumA<=70-cntA;
end if;
if(cntB<20) then -- 前20s支干道紅燈亮
RedB<='1';
GreenB<='0';
YellowB<='0';
NumB<=20-cntB;
elsif(cntB<50) then --21-50s支干道綠燈亮
RedB<='0';
GreenB<='1';
YellowB<='0';
NumB<=50-cntB;
else --51-60s支干道黃燈亮
RedB<='0';
GreenB<='0';
YellowB<='1';
NumB<=60-cntB;
end if;
end if;
end process;
end rtl;
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