library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY CTRO IS
  PORT(CLKK : IN STD_LOGIC;
       CNT_EN,LOAD,RST_CNT : OUT STD_LOGIC);
END CTRO;
ARCHITECTURE BEHAV OF CTRO IS
 signal div2clk:std_logic;
BEGIN
  PROCESS(CLKK)
  BEGIN 
    IF CLKK'EVENT AND CLKK='1' THEN
     div2clk <= not div2clk;
    end if;
  END PROCESS;
  process (clkK,div2clk)
  begin
   IF  CLKK='0' AND DIV2CLK='0' THEN RST_CNT<='1';
    ELSE RST_CNT<='0';
   END IF;
  END PROCESS;
  LOAD <= NOT DIV2CLK;
  CNT_EN <= DIV2CLK;
END BEHAV;