library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fttop IS
  PORT(CLK,Fin : in STD_LOGIC;
       q_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END ENTITY fttop;
ARCHITECTURE STRUC OF fttop IS
  component conter8
  PORT(CLK,RST,EN : IN STD_LOGIC;
              CQ : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
   end component;
   component cotal
  PORT(lock : IN STD_LOGIC;
       d : in STD_LOGIC_VECTOR(31 DOWNTO 0);
       q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
   end component;
   component ctro
  PORT(CLKK : IN STD_LOGIC;
       CNT_EN,LOAD,RST_CNT : OUT STD_LOGIC);
   end component;
signal a,b,c : STD_LOGIC;
signal v : STD_LOGIC_VECTOR(31 DOWNTO 0) ;
 BEGIN 
  u1 : ctro port map(clkK=>clk,CNT_EN=>a,LOAD=>b,RST_CNT=>c);
  u2 : conter8 port map(clk=>Fin,CQ=>v,RST=>c,EN=>a);
  u3 : cotal port map (lock=>b,d=>v,q=>q_out);
end ARCHITECTURE STRUC;