?? hdllib.ref
字號:
AR clockdiv_tbw testbench_arch D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv_tbw.vhw sub00/vhpl03 1181703562
EN clockdiv NULL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd sub00/vhpl00 1181702992
AR clockdiv behavioral D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd sub00/vhpl01 1181702993
EN clockdiv_tbw NULL D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv_tbw.vhw sub00/vhpl02 1181703561
MO glbl NULL C:/Xilinx/verilog/src/glbl.v vlg2D/glbl.bin 1181703560
MO ClockDiv NULL D:\MY_DESIGN\ISE\LXJ\ClockDiv/netgen/par/ClockDiv_timesim.v vlg27/_clock_div.bin 1181703558
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