Release 8.2i - xst I.31Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s --> Reading design: ClockDiv.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) Design Hierarchy Analysis  4) HDL Analysis  5) HDL Synthesis     5.1) HDL Synthesis Report  6) Advanced HDL Synthesis     6.1) Advanced HDL Synthesis Report  7) Low Level Synthesis  8) Partition Report  9) Final Report     9.1) Device utilization summary     9.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "ClockDiv.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "ClockDiv"Output Format                      : NGCTarget Device                      : xc2s200-5-fg256---- Source OptionsTop Module Name                    : ClockDivAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESSlice Packing                      : YESPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NORTL Output                         : YesGlobal Optimization                : AllClockNetsWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : ClockDiv.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOtristate2logic                     : Yesuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yes==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd" in Library work.Architecture behavioral of Entity clockdiv is up to date.=========================================================================*                     Design Hierarchy Analysis                         *=========================================================================Analyzing hierarchy for entity <ClockDiv> in library <work> (architecture <behavioral>).Building hierarchy successfully finished.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <ClockDiv> in library <work> (Architecture <behavioral>).Entity <ClockDiv> analyzed. Unit <ClockDiv> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <ClockDiv>.    Related source file is "D:/MY_DESIGN/ISE/LXJ/ClockDiv/ClockDiv.vhd".    Found 1-bit register for signal <clkdiv>.    Found 4-bit up counter for signal <cnt>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <ClockDiv> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Counters                                             : 1 4-bit up counter                                      : 1# Registers                                            : 1 1-bit register                                        : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================Loading device for application Rf_Device from file 'v200.nph' in environment C:\Xilinx.=========================================================================Advanced HDL Synthesis ReportMacro Statistics# Counters                                             : 1 4-bit up counter                                      : 1# Registers                                            : 1 Flip-Flops                                            : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <ClockDiv> ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block ClockDiv, actual ratio is 0.Final Macro Processing ...=========================================================================Final Register ReportMacro Statistics# Registers                                            : 5 Flip-Flops                                            : 5==================================================================================================================================================*                          Partition Report                             *=========================================================================Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : ClockDiv.ngrTop Level Output File Name         : ClockDivOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 3Cell Usage :# BELS                             : 6#      INV                         : 1#      LUT3                        : 1#      LUT4                        : 3#      VCC                         : 1# FlipFlops/Latches                : 5#      FDC                         : 4#      FDR                         : 1# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 2#      IBUF                        : 1#      OBUF                        : 1=========================================================================Device utilization summary:---------------------------Selected Device : 2s200fg256-5  Number of Slices:                       3  out of   2352     0%   Number of Slice Flip Flops:             5  out of   4704     0%   Number of 4 input LUTs:                 5  out of   4704     0%   Number of IOs:                          3 Number of bonded IOBs:                  3  out of    180     1%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 5     |-----------------------------------+------------------------+-------+Asynchronous Control Signals Information:---------------------------------------------------------------------------+------------------------+-------+Control Signal                     | Buffer(FF name)        | Load  |-----------------------------------+------------------------+-------+reset                              | IBUF                   | 4     |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5   Minimum period: 5.618ns (Maximum Frequency: 177.999MHz)   Minimum input arrival time before clock: No path found   Maximum output required time after clock: 7.999ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk'  Clock period: 5.618ns (frequency: 177.999MHz)  Total number of paths / destination ports: 16 / 5-------------------------------------------------------------------------Delay:               5.618ns (Levels of Logic = 1)  Source:            cnt_0 (FF)  Destination:       clkdiv (FF)  Source Clock:      clk rising  Destination Clock: clk rising  Data Path: cnt_0 to clkdiv                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDC:C->Q              5   1.292   1.740  cnt_0 (cnt_0)     LUT4:I2->O            1   0.653   1.150  _not00011 (_not0001)     FDR:R                     0.783          clkdiv    ----------------------------------------    Total                      5.618ns (2.728ns logic, 2.890ns route)                                       (48.6% logic, 51.4% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'  Total number of paths / destination ports: 1 / 1-------------------------------------------------------------------------Offset:              7.999ns (Levels of Logic = 1)  Source:            clkdiv (FF)  Destination:       clkdiv (PAD)  Source Clock:      clk rising  Data Path: clkdiv to clkdiv                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDR:C->Q              1   1.292   1.150  clkdiv (clkdiv_OBUF)     OBUF:I->O                 5.557          clkdiv_OBUF (clkdiv)    ----------------------------------------    Total                      7.999ns (6.849ns logic, 1.150ns route)                                       (85.6% logic, 14.4% route)=========================================================================CPU : 6.22 / 6.52 s | Elapsed : 6.00 / 6.00 s --> Total memory usage is 123364 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)