---------------------------------------------------------------------------------- Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.----------------------------------------------------------------------------------   ____  ____--  /   /\/   /-- /___/  \  /    Vendor: Xilinx-- \   \   \/     Version: I.31--  \   \         Application: netgen--  /   /         Filename: ClockDiv_map.vhd-- /___/   /\     Timestamp: Wed Jun 13 11:02:56 2007-- \   \  /  \ --  \___\/\___\--             -- Command	: -intstyle ise -s 5 -pcf ClockDiv.pcf -rpw 100 -tpw 0 -ar Structure -tm ClockDiv -w -dir netgen/map -ofmt vhdl -sim ClockDiv_map.ncd ClockDiv_map.vhd -- Device	: 2s200fg256-5 (PRODUCTION 1.27 2006-05-03)-- Input file	: ClockDiv_map.ncd-- Output file	: D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\map\ClockDiv_map.vhd-- # of Entities	: 1-- Design Name	: ClockDiv-- Xilinx	: C:\Xilinx--             -- Purpose:    --     This VHDL netlist is a verification model and uses simulation --     primitives which may not represent the true implementation of the --     device, however the netlist is functionally correct and should not --     be modified. This file cannot be synthesized and should only be used --     with supported simulation tools.--             -- Reference:  --     Development System Reference Guide, Chapter 23--     Synthesis and Simulation Design Guide, Chapter 6--             --------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity ClockDiv is  port (    clk : in STD_LOGIC := 'X';     reset : in STD_LOGIC := 'X';     clkdiv : out STD_LOGIC   );end ClockDiv;architecture Structure of ClockDiv is  signal clk_BUFGP : STD_LOGIC;   signal Q_not0001_0 : STD_LOGIC;   signal reset_IBUF_0 : STD_LOGIC;   signal clkdiv_OUTMUX_1 : STD_LOGIC;   signal clkdiv_OBUF_2 : STD_LOGIC;   signal clkdiv_LOGIC_ONE_3 : STD_LOGIC;   signal reset_IBUF_4 : STD_LOGIC;   signal cnt_3_FFX_RST : STD_LOGIC;   signal Q_not0001 : STD_LOGIC;   signal cnt_1_BYMUXNOT : STD_LOGIC;   signal cnt_3_FFY_RST : STD_LOGIC;   signal cnt_1_FFY_RST : STD_LOGIC;   signal cnt_1_FFX_RST : STD_LOGIC;   signal VCC : STD_LOGIC;   signal GND : STD_LOGIC;   signal cnt : STD_LOGIC_VECTOR ( 3 downto 0 );   signal Result : STD_LOGIC_VECTOR ( 3 downto 1 ); begin  clkdiv_LOGIC_ONE : X_ONE    port map (      O => clkdiv_LOGIC_ONE_3    );  clkdiv_OBUF : X_OBUF    port map (      I => clkdiv_OUTMUX_1,      O => clkdiv    );  clkdiv_OUTMUX : X_BUF    port map (      I => clkdiv_OBUF_2,      O => clkdiv_OUTMUX_1    );  reset_IMUX : X_BUF    port map (      I => reset_IBUF_4,      O => reset_IBUF_0    );  reset_IBUF : X_BUF    port map (      I => reset,      O => reset_IBUF_4    );  Mcount_cnt_xor_3_11 : X_LUT4    generic map(      INIT => X"6CC4"    )    port map (      ADR0 => cnt(0),      ADR1 => cnt(3),      ADR2 => cnt(1),      ADR3 => cnt(2),      O => Result(3)    );  Mcount_cnt_xor_2_11 : X_LUT4    generic map(      INIT => X"6A6A"    )    port map (      ADR0 => cnt(2),      ADR1 => cnt(1),      ADR2 => cnt(0),      ADR3 => VCC,      O => Result(2)    );  cnt_3 : X_FF    generic map(      INIT => '0'    )    port map (      I => Result(3),      CE => VCC,      CLK => clk_BUFGP,      SET => GND,      RST => cnt_3_FFX_RST,      O => cnt(3)    );  cnt_3_FFX_RSTOR : X_BUF    port map (      I => reset_IBUF_0,      O => cnt_3_FFX_RST    );  Mcount_cnt_xor_1_11 : X_LUT4    generic map(      INIT => X"6466"    )    port map (      ADR0 => cnt(0),      ADR1 => cnt(1),      ADR2 => cnt(2),      ADR3 => cnt(3),      O => Result(1)    );  Q_not00011 : X_LUT4    generic map(      INIT => X"FFBF"    )    port map (      ADR0 => cnt(1),      ADR1 => cnt(3),      ADR2 => cnt(0),      ADR3 => cnt(2),      O => Q_not0001    );  cnt_1_YUSED : X_BUF    port map (      I => Q_not0001,      O => Q_not0001_0    );  cnt_1_BYMUX : X_INV    port map (      I => cnt(0),      O => cnt_1_BYMUXNOT    );  clkdiv_0 : X_SFF    generic map(      INIT => '0'    )    port map (      I => clkdiv_LOGIC_ONE_3,      CE => VCC,      CLK => clk_BUFGP,      SET => GND,      RST => GND,      SSET => GND,      SRST => Q_not0001_0,      O => clkdiv_OBUF_2    );  cnt_2 : X_FF    generic map(      INIT => '0'    )    port map (      I => Result(2),      CE => VCC,      CLK => clk_BUFGP,      SET => GND,      RST => cnt_3_FFY_RST,      O => cnt(2)    );  cnt_3_FFY_RSTOR : X_BUF    port map (      I => reset_IBUF_0,      O => cnt_3_FFY_RST    );  cnt_0 : X_FF    generic map(      INIT => '0'    )    port map (      I => cnt_1_BYMUXNOT,      CE => VCC,      CLK => clk_BUFGP,      SET => GND,      RST => cnt_1_FFY_RST,      O => cnt(0)    );  cnt_1_FFY_RSTOR : X_BUF    port map (      I => reset_IBUF_0,      O => cnt_1_FFY_RST    );  cnt_1 : X_FF    generic map(      INIT => '0'    )    port map (      I => Result(1),      CE => VCC,      CLK => clk_BUFGP,      SET => GND,      RST => cnt_1_FFX_RST,      O => cnt(1)    );  cnt_1_FFX_RSTOR : X_BUF    port map (      I => reset_IBUF_0,      O => cnt_1_FFX_RST    );  clk_BUFGP_BUFG_BUF : X_CKBUF    port map (      I => clk,      O => clk_BUFGP    );  NlwBlock_ClockDiv_VCC : X_ONE    port map (      O => VCC    );  NlwBlock_ClockDiv_GND : X_ZERO    port map (      O => GND    );  NlwBlockROC : X_ROC    generic map (ROC_WIDTH => 100 ns)    port map (O => GSR);  NlwBlockTOC : X_TOC    port map (O => GTS);end Structure;