---------------------------------------------------------------------------------- Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.----------------------------------------------------------------------------------   ____  ____--  /   /\/   /-- /___/  \  /    Vendor: Xilinx-- \   \   \/     Version: I.31--  \   \         Application: netgen--  /   /         Filename: ClockDiv_translate.vhd-- /___/   /\     Timestamp: Wed Jun 13 11:01:59 2007-- \   \  /  \ --  \___\/\___\--             -- Command	: -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm ClockDiv -w -dir netgen/translate -ofmt vhdl -sim ClockDiv.ngd ClockDiv_translate.vhd -- Device	: 2s200fg256-5-- Input file	: ClockDiv.ngd-- Output file	: D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\translate\ClockDiv_translate.vhd-- # of Entities	: 1-- Design Name	: ClockDiv-- Xilinx	: C:\Xilinx--             -- Purpose:    --     This VHDL netlist is a verification model and uses simulation --     primitives which may not represent the true implementation of the --     device, however the netlist is functionally correct and should not --     be modified. This file cannot be synthesized and should only be used --     with supported simulation tools.--             -- Reference:  --     Development System Reference Guide, Chapter 23--     Synthesis and Simulation Design Guide, Chapter 6--             --------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity ClockDiv is  port (    clk : in STD_LOGIC := 'X';     reset : in STD_LOGIC := 'X';     clkdiv : out STD_LOGIC   );end ClockDiv;architecture Structure of ClockDiv is  signal clk_BUFGP : STD_LOGIC;   signal reset_IBUF_3 : STD_LOGIC;   signal clkdiv_OBUF_4 : STD_LOGIC;   signal Q_not0001 : STD_LOGIC;   signal N1 : STD_LOGIC;   signal N8 : STD_LOGIC;   signal clk_BUFGP_IBUFG_5 : STD_LOGIC;   signal VCC : STD_LOGIC;   signal GND : STD_LOGIC;   signal cnt : STD_LOGIC_VECTOR ( 3 downto 0 );   signal Result : STD_LOGIC_VECTOR ( 3 downto 1 );   signal Mcount_cnt_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); begin  XST_VCC : X_ONE    port map (      O => N1    );  clkdiv_0 : X_SFF    generic map(      INIT => '0'    )    port map (      I => N1,      SRST => Q_not0001,      CLK => clk_BUFGP,      O => clkdiv_OBUF_4,      CE => VCC,      SET => GND,      RST => GND,      SSET => GND    );  cnt_0 : X_FF    generic map(      INIT => '0'    )    port map (      I => Mcount_cnt_lut(0),      RST => reset_IBUF_3,      CLK => clk_BUFGP,      O => cnt(0),      CE => VCC,      SET => GND    );  cnt_1 : X_FF    generic map(      INIT => '0'    )    port map (      I => Result(1),      RST => reset_IBUF_3,      CLK => clk_BUFGP,      O => cnt(1),      CE => VCC,      SET => GND    );  cnt_2 : X_FF    generic map(      INIT => '0'    )    port map (      I => Result(2),      RST => reset_IBUF_3,      CLK => clk_BUFGP,      O => cnt(2),      CE => VCC,      SET => GND    );  cnt_3 : X_FF    generic map(      INIT => '0'    )    port map (      I => Result(3),      RST => reset_IBUF_3,      CLK => clk_BUFGP,      O => cnt(3),      CE => VCC,      SET => GND    );  Mcount_cnt_xor_2_11 : X_LUT3    generic map(      INIT => X"6A"    )    port map (      ADR0 => cnt(2),      ADR1 => cnt(1),      ADR2 => cnt(0),      O => Result(2)    );  Mcount_cnt_xor_1_11 : X_LUT4    generic map(      INIT => X"6466"    )    port map (      ADR0 => cnt(0),      ADR1 => cnt(1),      ADR2 => cnt(2),      ADR3 => cnt(3),      O => Result(1)    );  Mcount_cnt_xor_3_11 : X_LUT4    generic map(      INIT => X"6CC4"    )    port map (      ADR0 => cnt(0),      ADR1 => cnt(3),      ADR2 => cnt(1),      ADR3 => cnt(2),      O => Result(3)    );  Q_not00011 : X_LUT4    generic map(      INIT => X"FFBF"    )    port map (      ADR0 => cnt(1),      ADR1 => cnt(3),      ADR2 => cnt(0),      ADR3 => cnt(2),      O => Q_not0001    );  reset_IBUF : X_BUF    port map (      I => reset,      O => reset_IBUF_3    );  Mcount_cnt_lut_0_1_INV_0 : X_INV    port map (      I => cnt(0),      O => Mcount_cnt_lut(0)    );  XST_GND : X_ZERO    port map (      O => N8    );  clk_BUFGP_BUFG : X_CKBUF    port map (      I => clk_BUFGP_IBUFG_5,      O => clk_BUFGP    );  clk_BUFGP_IBUFG : X_CKBUF    port map (      I => clk,      O => clk_BUFGP_IBUFG_5    );  clkdiv_OBUF : X_OBUF    port map (      I => clkdiv_OBUF_4,      O => clkdiv    );  NlwBlock_ClockDiv_VCC : X_ONE    port map (      O => VCC    );  NlwBlock_ClockDiv_GND : X_ZERO    port map (      O => GND    );  NlwBlockROC : X_ROC    generic map (ROC_WIDTH => 100 ns)    port map (O => GSR);  NlwBlockTOC : X_TOC    port map (O => GTS);end Structure;