Release 8.2i - netgen I.31Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.Command Line: netgen -intstyle ise -s 5 -pcf ClockDiv.pcf -rpw 100 -tpw 0 -ar
Structure -tm ClockDiv -w -dir netgen/par -ofmt vhdl -sim ClockDiv.ncd
ClockDiv_timesim.vhd  Read and Annotate design 'ClockDiv.ncd' ...Loading device for application Rf_Device from file 'v200.nph' in environment
C:\Xilinx.   "ClockDiv" is an NCD, version 3.1, device xc2s200, package fg256, speed -5Loading constraints from 'ClockDiv.pcf'...The speed grade (-5) differs from the speed grade specified in the .ncd file
(-5).The number of routable networks is 8Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing VHDL netlist
'D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\par\ClockDiv_timesim.vhd' ...Writing VHDL SDF file
'D:\MY_DESIGN\ISE\LXJ\ClockDiv\netgen\par\ClockDiv_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 93240 kilobytes