Release 8.2i par I.31Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.D18C9N1X::  Wed Jun 13 16:29:50 2007par -w -intstyle ise -ol std -t 1 decoder24_map.ncd decoder24.ncd decoder24.pcfConstraints file: decoder24.pcf.Loading device for application Rf_Device from file 'v100.nph' in environment C:\Xilinx.   "decoder24" is an NCD, version 3.1, device xc2s100, package tq144, speed -6Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".Device speed data version:  "PRODUCTION 1.27 2006-05-03".Device Utilization Summary:   Number of External IOBs             6 out of 92      6%      Number of LOCed IOBs             6 out of 6     100%   Number of SLICEs                    4 out of 1200    1%      Number of LOCed SLICEs           4 out of 4     100%Overall effort level (-ol):   Standard Placer effort level (-pl):    High Placer cost table entry (-t): 1Router effort level (-rl):    Standard Starting PlacerPhase 1.1Phase 1.1 (Checksum:989693) REAL time: 5 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs Phase 3.23Phase 3.23 (Checksum:1c9c37d) REAL time: 5 secs Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 5 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs Phase 6.8Phase 6.8 (Checksum:98a48f) REAL time: 5 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 5 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 5 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 5 secs Writing design to file decoder24.ncdTotal REAL time to Placer completion: 6 secs Total CPU time to Placer completion: 2 secs Starting RouterPhase 1: 12 unrouted;       REAL time: 7 secs Phase 2: 12 unrouted;       REAL time: 7 secs Phase 3: 0 unrouted;       REAL time: 7 secs Phase 4: 0 unrouted; (0)      REAL time: 7 secs Phase 5: 0 unrouted; (0)      REAL time: 7 secs Phase 6: 0 unrouted; (0)      REAL time: 7 secs Total REAL time to Router completion: 7 secs Total CPU time to Router completion: 2 secs Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Generating "PAR" statistics.   The Delay Summary ReportThe NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.982   The MAXIMUM PIN DELAY IS:                               1.707   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.057   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------           5           7           0           0           0           0Timing Score: 0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 9 secs Total CPU time to PAR completion: 3 secs Peak Memory Usage:  112 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file decoder24.ncdPAR done!