library verilog;use verilog.vl_types.all;entity sub_cf is    port(        a               : in     vl_logic_vector(3 downto 0);        b               : in     vl_logic_vector(3 downto 0);        \out\           : out    vl_logic_vector(3 downto 0);        CF              : out    vl_logic    );end sub_cf;