library verilog;use verilog.vl_types.all;entity pa_se is    port(        clk             : in     vl_logic_vector(0 downto 0);        \in\            : in     vl_logic_vector(3 downto 0);        \out\           : out    vl_logic_vector(0 downto 0);        clr             : in     vl_logic_vector(0 downto 0)    );end pa_se;