?? i2c.gfl
字號:
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXST
i2c_master_bit_ctrl.syr
i2c_master_bit_ctrl.prj
i2c_master_bit_ctrl.sprj
i2c_master_bit_ctrl.ana
i2c_master_bit_ctrl.stx
i2c_master_bit_ctrl.cmd_log
i2c_master_bit_ctrl.ngc
i2c_master_bit_ctrl.ngr
# ModelSim : Simulate Behavioral Verilog Model
i2c_slave_model.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Post-Translate VHDL Model
i2c_slave_model.ndo
# ModelSim : Simulate Post-Translate Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) :
i2c_master_byte_ctrl.lso
# Check Syntax
i2c_master_byte_ctrl.stx
i2c_master_bit_ctrl.ngc
# xst flow : RunXST
i2c_master_byte_ctrl.syr
i2c_master_byte_ctrl.prj
i2c_master_byte_ctrl.sprj
i2c_master_byte_ctrl.ana
i2c_master_byte_ctrl.stx
i2c_master_byte_ctrl.cmd_log
i2c_master_bit_ctrl.ngc
i2c_master_byte_ctrl.ngc
i2c_master_bit_ctrl.ngr
i2c_master_byte_ctrl.ngr
# xst flow : RunXST
i2c_master_top.syr
i2c_master_top.prj
i2c_master_top.sprj
i2c_master_top.ana
i2c_master_top.stx
i2c_master_top.cmd_log
i2c_master_bit_ctrl.ngc
i2c_master_byte_ctrl.ngc
i2c_master_top.ngc
i2c_master_bit_ctrl.ngr
i2c_master_byte_ctrl.ngr
i2c_master_top.ngr
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