WARNING:HDLCompilers:38 - i2c_master_defines.v line 60 Macro 'I2C_CMD_NOP' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 61 Macro 'I2C_CMD_START' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 62 Macro 'I2C_CMD_STOP' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 63 Macro 'I2C_CMD_WRITE' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 64 Macro 'I2C_CMD_READ' redefinedModule <i2c_master_byte_ctrl> compiledCompiling source file "i2c_master_top.v"Compiling include file "i2c_master_defines.v"WARNING:HDLCompilers:38 - i2c_master_defines.v line 60 Macro 'I2C_CMD_NOP' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 61 Macro 'I2C_CMD_START' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 62 Macro 'I2C_CMD_STOP' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 63 Macro 'I2C_CMD_WRITE' redefinedWARNING:HDLCompilers:38 - i2c_master_defines.v line 64 Macro 'I2C_CMD_READ' redefinedModule <i2c_master_top> compiledNo errors in compilationAnalysis of file <i2c_master_top.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <i2c_master_top>.WARNING:Xst:916 - i2c_master_top.v line 153: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_top.v line 174: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_top.v line 175: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_top.v line 176: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_top.v line 180: Delay is ignored for synthesis.WARNING:Xst:915 - Message (916) is reported only 5 times for each module.Module <i2c_master_top> is correct for synthesis. Analyzing module <i2c_master_byte_ctrl>.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 168: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 170: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 172: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 174: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_byte_ctrl.v line 179: Delay is ignored for synthesis.WARNING:Xst:915 - Message (916) is reported only 5 times for each module.Module <i2c_master_byte_ctrl> is correct for synthesis. Analyzing module <i2c_master_bit_ctrl>.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 180: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 189: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 190: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 194: Delay is ignored for synthesis.WARNING:Xst:916 - i2c_master_bit_ctrl.v line 195: Delay is ignored for synthesis.WARNING:Xst:915 - Message (916) is reported only 5 times for each module.Module <i2c_master_bit_ctrl> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <i2c_master_bit_ctrl>.    Related source file is i2c_master_bit_ctrl.v.    Found finite state machine <FSM_0> for signal <c_state>.    -----------------------------------------------------------------------    | States             | 18                                             |    | Transitions        | 50                                             |    | Inputs             | 6                                              |    | Outputs            | 19                                             |    | Clock              | clk (rising_edge)                              |    | Clock enable       | $n0001 (positive)                              |    | Reset              | nReset (negative)                              |    | Reset type         | asynchronous                                   |    | Reset State        | 000000000000000001                             |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <sda_oen>.    Found 1-bit register for signal <al>.    Found 1-bit register for signal <cmd_ack>.    Found 1-bit register for signal <busy>.    Found 1-bit register for signal <scl_oen>.    Found 1-bit register for signal <dout>.    Found 16-bit subtractor for signal <$n0049> created at line 210.    Found 1-bit register for signal <clk_en>.    Found 1-bit register for signal <cmd_stop>.    Found 16-bit register for signal <cnt>.    Found 1-bit register for signal <dcmd_stop>.    Found 1-bit register for signal <dSCL>.    Found 1-bit register for signal <dscl_oen>.    Found 1-bit register for signal <dSDA>.    Found 1-bit register for signal <sda_chk>.    Found 1-bit register for signal <sSCL>.    Found 1-bit register for signal <sSDA>.    Found 1-bit register for signal <sta_condition>.    Found 1-bit register for signal <sto_condition>.    Summary:	inferred   1 Finite State Machine(s).	inferred  33 D-type flip-flop(s).	inferred   1 Adder/Subtracter(s).Unit <i2c_master_bit_ctrl> synthesized.Synthesizing Unit <i2c_master_byte_ctrl>.    Related source file is i2c_master_byte_ctrl.v.    Found finite state machine <FSM_1> for signal <c_state>.    -----------------------------------------------------------------------    | States             | 6                                              |    | Transitions        | 31                                             |    | Inputs             | 9                                              |    | Outputs            | 6                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | nReset (negative)                              |    | Reset type         | asynchronous                                   |    | Reset State        | 000001                                         |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <cmd_ack>.    Found 1-bit register for signal <ack_out>.    Found 3-bit subtractor for signal <$n0021> created at line 185.    Found 4-bit register for signal <core_cmd>.    Found 1-bit register for signal <core_txd>.    Found 3-bit register for signal <dcnt>.    Found 1-bit register for signal <ld>.    Found 1-bit register for signal <shift>.    Found 8-bit register for signal <sr>.    Summary:	inferred   1 Finite State Machine(s).	inferred  20 D-type flip-flop(s).	inferred   1 Adder/Subtracter(s).Unit <i2c_master_byte_ctrl> synthesized.Synthesizing Unit <i2c_master_top>.    Related source file is i2c_master_top.v.    Found 8-bit register for signal <wb_dat_o>.    Found 1-bit register for signal <wb_inta_o>.    Found 1-bit register for signal <wb_ack_o>.    Found 8-bit 8-to-1 multiplexer for signal <$n0003> created at line 158.    Found 1-bit register for signal <al>.    Found 8-bit register for signal <cr>.    Found 8-bit register for signal <ctr>.    Found 1-bit register for signal <irq_flag>.    Found 16-bit register for signal <prer>.    Found 1-bit register for signal <rxack>.    Found 1-bit register for signal <tip>.    Found 8-bit register for signal <txr>.    Summary:	inferred  54 D-type flip-flop(s).	inferred   8 Multiplexer(s).Unit <i2c_master_top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# FSMs                             : 2# Registers                        : 59  1-bit register                   : 52  4-bit register                   : 1  8-bit register                   : 4  16-bit register                  : 1  3-bit register                   : 1# Multiplexers                     : 1  8-bit 8-to-1 multiplexer         : 1# Adders/Subtractors               : 2  16-bit subtractor                : 1  3-bit subtractor                 : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================Selecting encoding for FSM_1 ...Optimizing FSM <FSM_1> on signal <c_state> with one-hot encoding.Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <c_state> with one-hot encoding.=========================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <i2c_master_top> ...Optimizing unit <i2c_master_bit_ctrl> ...Optimizing unit <i2c_master_byte_ctrl> ...Loading device for application Xst from file '2s50e.nph' in environment C:/Program Files/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block i2c_master_top, actual ratio is 17.FlipFlop byte_controller_bit_controller_al has been replicated 1 time(s)FlipFlop wb_ack_o has been replicated 1 time(s) to handle iob=true attribute.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50etq144-6  Number of Slices:                     134  out of    768    17%   Number of Slice Flip Flops:           133  out of   1536     8%   Number of 4 input LUTs:               243  out of   1536    15%   Number of bonded IOBs:                 32  out of    102    31%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+wb_clk_i                           | BUFGP                  | 133   |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6   Minimum period: 9.441ns (Maximum Frequency: 105.921MHz)   Minimum input arrival time before clock: 11.700ns   Maximum output required time after clock: 6.914ns   Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".