Fitter report for clock
Wed Dec 14 14:45:24 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. All Package Pins
 11. I/O Standard
 12. Dedicated Inputs I/O
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB External Interconnect
 20. LAB Macrocells
 21. Parallel Expander
 22. Shareable Expander
 23. Logic Cell Interconnection
 24. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Wed Dec 14 14:45:24 2005    ;
; Quartus II Version    ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name         ; clock                                    ;
; Top-level Entity Name ; clock                                    ;
; Family                ; MAX7000S                                 ;
; Device                ; EPM7128SLC84-15                          ;
; Timing Models         ; Final                                    ;
; Total macrocells      ; 95 / 128 ( 74 % )                        ;
; Total pins            ; 22 / 68 ( 32 % )                         ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------+
; Fitter Settings                                                                      ;
+--------------------------------------------+--------------------+--------------------+
; Option                                     ; Setting            ; Default Value      ;
+--------------------------------------------+--------------------+--------------------+
; Device                                     ; EPM7128SLC84-15    ;                    ;
; Fitter Effort                              ; Standard Fit       ; Auto Fit           ;
; Use smart compilation                      ; Off                ; Off                ;
; Optimize Timing                            ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On                 ; On                 ;
; Limit to One Fitting Attempt               ; Off                ; Off                ;
; Fitter Initial Placement Seed              ; 1                  ; 1                  ;
; Slow Slew Rate                             ; Off                ; Off                ;
+--------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Security bit                                 ; Off                 ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/數字時鐘/clock.fit.eqn.


+--------------+
; Pin-Out File ;