{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(90) " "Warning: Verilog HDL assignment warning at traffic.v(90): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 90 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(91) " "Warning: Verilog HDL assignment warning at traffic.v(91): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 91 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 traffic.v(118) " "Warning: Verilog HDL assignment warning at traffic.v(118): truncated value with size 32 to match size of target (16)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 traffic.v(121) " "Warning: Verilog HDL assignment warning at traffic.v(121): truncated value with size 32 to match size of target (16)" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 121 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "traffic.v(129) " "Info: Verilog HDL Case Statement information at traffic.v(129): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 129 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_scan\[0\]~0 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_scan\[0\]~0\"" {  } { { "traffic.v" "cnt_scan\[0\]~0" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|traffic\|state 3 0 " "Info: State machine \"\|traffic\|state\" contains 3 states and 0 state bits" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|traffic\|state " "Info: Selected Auto state machine encoding method for state machine \"\|traffic\|state\"" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|traffic\|state " "Info: Encoding result for state machine \"\|traffic\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "2 " "Info: Completed encoding using 2 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state~48 " "Info: Encoded state bit \"state~48\"" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state~47 " "Info: Encoded state bit \"state~47\"" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|state.red 00 " "Info: State \"\|traffic\|state.red\" uses code string \"00\"" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|state.green 10 " "Info: State \"\|traffic\|state.green\" uses code string \"10\"" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|traffic\|state.yellow 01 " "Info: State \"\|traffic\|state.yellow\" uses code string \"01\"" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0}  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 20 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "26 " "Info: Ignored 26 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "26 " "Info: Ignored 26 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 19 -1 0 } } { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 11 -1 0 } } { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "second\[3\] data_in GND " "Warning: Reduced register \"second\[3\]\" with stuck data_in port to stuck value GND" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 19 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "traffic.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/綜合實驗/交通燈/traffic.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "90 " "Info: Implemented 90 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "74 " "Info: Implemented 74 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 14:42:50 2005 " "Info: Processing ended: Wed Dec 14 14:42:50 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}