library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_arith.all;use work.baseball_pkg.all;entity baseball_led_out is    port (    clk, resetn                               : in  std_logic;    team                              : in  std_logic;    base1, base2, base3                        : in  std_logic;    add_to_score1, add_to_score2, add_to_score3, add_to_score4: in std_logic;    base1_led, base2_led, base3_led, team_led0, team_led1 : out std_logic;    score0_led, score1_led : out std_logic_vector(7 downto 0));end baseball_led_out;architecture rtl of baseball_led_out is  signal score0_ff, score1_ff : std_logic_vector(3 downto 0);  signal score0_led_node,score1_led_node : std_logic_vector(7 downto 0);  signal score_adder_dataa, score_adder_datab : std_logic_vector(3 downto 0);  begin  -- rtl  process (clk, resetn)  begin  -- process    if resetn = '0' then                -- asynchronous reset (active low)      score0_ff <= (others => '0');      score1_ff <= (others => '0');    elsif clk'event and clk = '1' then  -- rising clock edge      if ((add_to_score1 or add_to_score2 or add_to_score3 or add_to_score4) and not team)= '1' then        score0_ff <= score_adder_dataa + score_adder_datab;      end if;      if ((add_to_score1 or add_to_score2 or add_to_score3 or add_to_score4) and team) = '1' then        score1_ff <= score_adder_dataa + score_adder_datab;      end if;    end if;  end process;  process (team, score0_ff, score1_ff, add_to_score1, add_to_score2, add_to_score3, add_to_score4)  begin  -- process    if team = '1' then      score_adder_dataa <=  score1_ff;    else      score_adder_dataa <=  score0_ff;    end if;        if add_to_score1 = '1' then      score_adder_datab <= conv_std_logic_vector(1,4);    elsif add_to_score2 = '1' then      score_adder_datab <=  conv_std_logic_vector(2,4);    elsif add_to_score3 =  '1' then      score_adder_datab <=  conv_std_logic_vector(3,4);    elsif add_to_score4 =  '1' then      score_adder_datab <=  conv_std_logic_vector(4,4);    else      score_adder_datab <= (others => '0');     end if;  end process;    process(team, base1, base2, base3)  begin  -- process    team_led0 <= not team;    team_led1 <= team;        base1_led <= not base1;    base2_led <= not base2;    base3_led <= not base3;  end process;  score0_led <= score0_led_node;  score1_led <= score1_led_node;    -- decode to output to 7 sgment LED  score0_led_node <= LED_dec(score0_ff);  score1_led_node <= LED_dec(score1_ff);end rtl;