library ieee;
use ieee.std_logic_1164.all;

entity base is
  port (clk,hit1,hit2,hit3,hit4,resetn: in std_logic;
        base1,base2,base3 : out std_logic);
end;

architecture behavior of base is
  type type_sreg is (no_runner,runner1,runner1_2,runner1_2_3,runner1_3,runner2,
                     runner2_3,runner3);
  signal sreg, next_sreg : type_sreg;
  signal next_base1,next_base2,next_base3 : std_logic;
begin
  process (clk, resetn)
  begin
    if resetn='0' then
      sreg <= no_runner;
      base1 <= '0';
      base2 <= '0';
      base3 <= '0';
    elsif clk='1' and clk'event then
      sreg <= next_sreg;
      base1 <= next_base1;
      base2 <= next_base2;
      base3 <= next_base3;
    end if;
  end process;

  process (sreg,hit1,hit2,hit3,hit4)
  begin
    case sreg is
      when no_runner =>
        if  hit1='1'  then
          next_sreg<=runner1;
          next_base3<='0';
          next_base2<='0';
          next_base1<='1';
        elsif  hit2='1'  then
          next_sreg<=runner2;
          next_base3<='0';
          next_base1<='0';
          next_base2<='1';
        elsif  hit3='1'  then
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        else
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        end if;
      when runner1 =>
        if  hit2='1'  then
          next_sreg<=runner2_3;
          next_base1<='0';
          next_base2<='1';
          next_base3<='1';
        elsif  hit1='1'  then
          next_sreg<=runner1_2;
          next_base3<='0';
          next_base1<='1';
          next_base2<='1';
        elsif  hit4='1'  then
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        elsif  hit3='1'  then
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        else
          next_sreg<=runner1;
          next_base3<='0';
          next_base2<='0';
          next_base1<='1';
        end if;
      when runner1_2 =>
        if  hit4='1'  then
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        elsif  hit3='1'  then
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        elsif  hit2='1'  then
          next_sreg<=runner2_3;
          next_base1<='0';
          next_base2<='1';
          next_base3<='1';
        elsif  hit1='1'  then
          next_sreg<=runner1_2_3;
          next_base1<='1';
          next_base2<='1';
          next_base3<='1';
        else
          next_sreg<=runner1_2;
          next_base3<='0';
          next_base1<='1';
          next_base2<='1';
        end if;
      when runner1_2_3 =>
        if  hit4='1'  then
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        elsif  hit3='1'  then
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        elsif  hit2='1'  then
          next_sreg<=runner2_3;
          next_base1<='0';
          next_base2<='1';
          next_base3<='1';
        else
          next_sreg<=runner1_2_3;
          next_base1<='1';
          next_base2<='1';
          next_base3<='1';
        end if;
      when runner1_3 =>
        if  hit1='1'  then
          next_sreg<=runner1_2;
          next_base3<='0';
          next_base1<='1';
          next_base2<='1';
        elsif  hit3='1'  then
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        elsif  hit2='1'  then
          next_sreg<=runner2_3;
          next_base1<='0';
          next_base2<='1';
          next_base3<='1';
        elsif  hit4='1'  then
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        else
          next_sreg<=runner1_3;
          next_base2<='0';
          next_base1<='1';
          next_base3<='1';
        end if;
      when runner2 =>
        if  hit4='1'  then
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        elsif  hit3='1'  then
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        elsif  hit1='1'  then
          next_sreg<=runner1_3;
          next_base2<='0';
          next_base1<='1';
          next_base3<='1';
        else
          next_sreg<=runner2;
          next_base3<='0';
          next_base1<='0';
          next_base2<='1';
        end if;
      when runner2_3 =>
        if  hit3='1'  then
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        elsif  hit2='1'  then
          next_sreg<=runner2;
          next_base3<='0';
          next_base1<='0';
          next_base2<='1';
        elsif  hit4='1'  then
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        elsif  hit1='1'  then
          next_sreg<=runner1_3;
          next_base2<='0';
          next_base1<='1';
          next_base3<='1';
        else
          next_sreg<=runner2_3;
          next_base1<='0';
          next_base2<='1';
          next_base3<='1';
        end if;
      when runner3 =>
        if  hit4='1'  then
          next_sreg<=no_runner;
          next_base3<='0';
          next_base2<='0';
          next_base1<='0';
        elsif  hit2='1'  then
          next_sreg<=runner2;
          next_base3<='0';
          next_base1<='0';
          next_base2<='1';
        elsif  hit1='1'  then
          next_sreg<=runner1;
          next_base3<='0';
          next_base2<='0';
          next_base1<='1';
        else
          next_sreg<=runner3;
          next_base2<='0';
          next_base1<='0';
          next_base3<='1';
        end if;
      when others =>
    end case;
  end process;
end behavior;