library IEEE;use IEEE.std_logic_1164.all;entity batter_led_dec is    port (    hit1, hit2, hit3, hit4, out_in : in  std_logic;    batter_led                  : out std_logic_vector(7 downto 0));end batter_led_dec;architecture rtl of batter_led_dec isbegin  -- rtl  batter_led <= "01100000" when hit1 = '1' else                "11011010" when hit2 = '1' else                "11110010" when hit3 = '1' else                "01101110" when hit4 = '1' else                "11111100" when out_in = '1' else                "00000000";                end rtl;