-------------------------------------------------------------------------------  LEON3 Demonstration design--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License as published by--  the Free Software Foundation; either version 2 of the License, or--  (at your option) any later version.----  This program is distributed in the hope that it will be useful,--  but WITHOUT ANY WARRANTY; without even the implied warranty of--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the--  GNU General Public License for more details.----  You should have received a copy of the GNU General Public License--  along with this program; if not, write to the Free Software--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library grlib;use grlib.amba.all;use grlib.stdlib.all;library techmap;use techmap.gencomp.all;library gaisler;use gaisler.memctrl.all;use gaisler.leon3.all;use gaisler.uart.all;use gaisler.misc.all;use gaisler.can.all;use gaisler.pci.all;use gaisler.net.all;use gaisler.jtag.all;use gaisler.spacewire.all;library esa;use esa.memoryctrl.all;use esa.pcicomp.all;use work.config.all;entity leon3mp is  generic (    fabtech   : integer := CFG_FABTECH;    memtech   : integer := CFG_MEMTECH;    padtech   : integer := CFG_PADTECH;    clktech   : integer := CFG_CLKTECH;    ncpu      : integer := CFG_NCPU;    disas     : integer := CFG_DISAS;	-- Enable disassembly to console    dbguart   : integer := CFG_DUART;	-- Print UART on console    pclow     : integer := CFG_PCLOW  );  port (    resetn	: in  std_ulogic;    clk		: in  std_ulogic;    pllref 	: in  std_ulogic;     errorn	: out std_ulogic;    address 	: out std_logic_vector(27 downto 0);    data	: inout std_logic_vector(31 downto 0);    sa      	: out std_logic_vector(14 downto 0);    sd   	: inout std_logic_vector(63 downto 0);    sdclk  	: out std_ulogic;    sdcke  	: out std_logic_vector (1 downto 0);    -- sdram clock enable    sdcsn  	: out std_logic_vector (1 downto 0);    -- sdram chip select    sdwen  	: out std_ulogic;                       -- sdram write enable    sdrasn  	: out std_ulogic;                       -- sdram ras    sdcasn  	: out std_ulogic;                       -- sdram cas    sddqm   	: out std_logic_vector (7 downto 0);    -- sdram dqm    dsutx  	: out std_ulogic; 			-- DSU tx data    dsurx  	: in  std_ulogic;  			-- DSU rx data    dsuen   	: in std_ulogic;    dsubre  	: in std_ulogic;    dsuact  	: out std_ulogic;    txd1   	: out std_ulogic; 			-- UART1 tx data    rxd1   	: in  std_ulogic;  			-- UART1 rx data    txd2   	: out std_ulogic; 			-- UART2 tx data    rxd2   	: in  std_ulogic;  			-- UART2 rx data    ramsn  	: out std_logic_vector (4 downto 0);    ramoen 	: out std_logic_vector (4 downto 0);    rwen   	: out std_logic_vector (3 downto 0);    oen    	: out std_ulogic;    writen 	: out std_ulogic;    read   	: out std_ulogic;    iosn   	: out std_ulogic;    romsn  	: out std_logic_vector (1 downto 0);    gpio        : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); 	-- I/O port    emdio     	: inout std_logic;		-- ethernet PHY interface    etx_clk 	: in std_ulogic;    erx_clk 	: in std_ulogic;    erxd    	: in std_logic_vector(3 downto 0);       erx_dv  	: in std_ulogic;     erx_er  	: in std_ulogic;     erx_col 	: in std_ulogic;    erx_crs 	: in std_ulogic;    etxd 	: out std_logic_vector(3 downto 0);       etx_en 	: out std_ulogic;     etx_er 	: out std_ulogic;     emdc 	: out std_ulogic;    emddis 	: out std_logic;        epwrdwn 	: out std_ulogic;    ereset 	: out std_ulogic;    esleep 	: out std_ulogic;    epause 	: out std_ulogic;    pci_rst     : in std_ulogic;		-- PCI bus    pci_clk 	: in std_ulogic;    pci_gnt     : in std_ulogic;    pci_idsel   : in std_ulogic;     pci_lock    : inout std_ulogic;    pci_ad 	: inout std_logic_vector(31 downto 0);    pci_cbe 	: inout std_logic_vector(3 downto 0);    pci_frame   : inout std_ulogic;    pci_irdy 	: inout std_ulogic;    pci_trdy 	: inout std_ulogic;    pci_devsel  : inout std_ulogic;    pci_stop 	: inout std_ulogic;    pci_perr 	: inout std_ulogic;    pci_par 	: inout std_ulogic;        pci_req 	: inout std_ulogic;    pci_serr    : inout std_ulogic;    pci_host   	: in std_ulogic;    pci_66	: in std_ulogic;    pci_arb_req	: in  std_logic_vector(0 to 3);    pci_arb_gnt	: out std_logic_vector(0 to 3);    can_txd	: out std_ulogic;    can_rxd	: in  std_ulogic;    can_stb	: out std_ulogic;    spw_clk	: in  std_ulogic;    spw_rxd     : in  std_logic_vector(0 to 2);    spw_rxdn    : in  std_logic_vector(0 to 2);    spw_rxs     : in  std_logic_vector(0 to 2);    spw_rxsn    : in  std_logic_vector(0 to 2);    spw_txd     : out std_logic_vector(0 to 2);    spw_txdn    : out std_logic_vector(0 to 2);    spw_txs     : out std_logic_vector(0 to 2);    spw_txsn    : out std_logic_vector(0 to 2);    tck, tms, tdi : in std_ulogic;    tdo         : out std_ulogic	);end;architecture rtl of leon3mp isconstant blength : integer := 12;constant maxahbmsp : integer := NCPU+CFG_AHB_UART+	CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;signal vcc, gnd : std_logic_vector(4 downto 0);signal memi  : memory_in_type;signal memo  : memory_out_type;signal wpo   : wprot_out_type;signal sdi   : sdctrl_in_type;signal sdo   : sdram_out_type;signal sdo2, sdo3 : sdctrl_out_type;signal apbi  : apb_slv_in_type;signal apbo  : apb_slv_out_vector := (others => apb_none);signal ahbsi : ahb_slv_in_type;signal ahbso : ahb_slv_out_vector := (others => ahbs_none);signal ahbmi : ahb_mst_in_type;signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);signal clkx, clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_ulogic;signal cgi   : clkgen_in_type;signal cgo   : clkgen_out_type;signal u1i, u2i, dui : uart_in_type;signal u1o, u2o, duo : uart_out_type;signal irqi : irq_in_vector(0 to NCPU-1);signal irqo : irq_out_vector(0 to NCPU-1);signal dbgi : l3_debug_in_vector(0 to NCPU-1);signal dbgo : l3_debug_out_vector(0 to NCPU-1);signal gclk : std_logic_vector(NCPU-1 downto 0);signal dsui : dsu_in_type;signal dsuo : dsu_out_type; signal pcii : pci_in_type;signal pcio : pci_out_type;signal ethi, ethi1, ethi2 : eth_in_type;signal etho, etho1, etho2 : eth_out_type;signal edcli : edcl_in_type;signal gpti : gptimer_in_type;signal gpioi : gpio_in_type;signal gpioo : gpio_out_type;signal can_lrx, can_ltx   : std_ulogic;signal lclk, pci_lclk : std_ulogic;signal pci_arb_req_n, pci_arb_gnt_n   : std_logic_vector(0 to 3);signal spwi : grspw_in_type_vector(0 to 2);signal spwo : grspw_out_type_vector(0 to 2);constant BOARD_FREQ : integer := 40000;	-- Board frequency in KHzconstant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;begin-------------------------------------------------------------------------  Reset and Clock generation  -----------------------------------------------------------------------------------------------------------    vcc <= (others => '1'); gnd <= (others => '0');  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;  pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);   clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);   pci_clk_pad : clkpad generic map (tech => padtech, level => pci33) 	    port map (pci_clk, pci_lclk);   clkgen0 : clkgen  		-- clock generator    generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN, 	CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)    port map (lclk, pci_lclk, clkx, open, open, sdclkl, pciclk, cgi, cgo);  clkpwd : entity work.clkgate generic map (fabtech, NCPU) 	port map (rstn, clkx, dsuo.pwd(NCPU-1 downto 0), clkm, gclk);  sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) 	port map (sdclk, sdclkl);  rst0 : rstgen			-- reset generator  port map (resetn, clkm, cgo.clklock, rstn, rstraw);-------------------------------------------------------------------------  AHB CONTROLLER ------------------------------------------------------------------------------------------------------------------------  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, 	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);-------------------------------------------------------------------------  LEON3 processor and DSU ---------------------------------------------------------------------------------------------------------------  l3 : if CFG_LEON3 = 1 generate    cpu : for i in 0 to NCPU-1 generate      u0 : leon3cg			-- LEON3 processor            generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 	0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, 	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,        CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,         CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED)      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,     		irqi(i), irqo(i), dbgi(i), dbgo(i), gclk(i));      nodsu : if CFG_DSU = 0 generate         dsuo.pwd(i) <= dbgo(i).pwd and not dbgo(i).ipend;      end generate;    end generate;    errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);      dsugen : if CFG_DSU = 1 generate      dsu0 : dsu3			-- LEON3 Debug Support Unit      generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,          ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)      port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);      dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);       dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);       dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);    end generate;  end generate;  nodsu : if CFG_DSU = 0 generate     ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';  end generate;  dcomgen : if CFG_AHB_UART = 1 generate    dcom0: ahbuart		-- Debug UART    generic map (hindex => NCPU, pindex => 7, paddr => 7)    port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));    dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);     dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);  end generate;  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;  ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate    ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)      port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),               open, open, open, open, open, open, open, gnd(0));  end generate;  -------------------------------------------------------------------------  Memory controllers --------------------------------------------------------------------------------------------------------------------  src : if CFG_SRCTRL = 1 generate	-- 32-bit PROM/SRAM controller    sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS, 	romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#, 	prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)    port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);    apbo(0) <= apb_none;  end generate;  sdc : if CFG_SDCTRL = 1 generate      sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#, 	ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK, 	sdbits => 32 + 32*CFG_SDCTRL_SD64)      port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);      sa_pad : outpadv generic map (width => 15, tech => padtech) 	   port map (sa, sdo2.address);      sd_pad : iopadv generic map (width => 32, tech => padtech) 	   port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));      sd2 : if CFG_SDCTRL_SD64 = 1 generate        sd_pad2 : iopadv generic map (width => 32) 	     port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));      end generate;      sdcke_pad : outpadv generic map (width =>2, tech => padtech) 	   port map (sdcke, sdo2.sdcke);       sdwen_pad : outpad generic map (tech => padtech) 	   port map (sdwen, sdo2.sdwen);      sdcsn_pad : outpadv generic map (width =>2, tech => padtech) 	   port map (sdcsn, sdo2.sdcsn);       sdras_pad : outpad generic map (tech => padtech) 	   port map (sdrasn, sdo2.rasn);      sdcas_pad : outpad generic map (tech => padtech) 	   port map (sdcasn, sdo2.casn);      sddqm_pad : outpadv generic map (width =>8, tech => padtech) 	   port map (sddqm, sdo2.dqm);  end generate;  mg2 : if CFG_MCTRL_LEON2 = 1 generate 	-- LEON2 memory controller    sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0, 	srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN, 	ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, 	invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS, 	sdbits => 32 + 32*CFG_MCTRL_SD64)    port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);    sdpads : if CFG_MCTRL_SDEN = 1 generate 	-- SDRAM controller      sd2 : if CFG_MCTRL_SEPBUS = 1 generate        sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);