--------------------------------------------------------------------------------  LEON3 Demonstration design test bench--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License as published by--  the Free Software Foundation; either version 2 of the License, or--  (at your option) any later version.----  This program is distributed in the hope that it will be useful,--  but WITHOUT ANY WARRANTY; without even the implied warranty of--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the--  GNU General Public License for more details.------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library grlib;use grlib.stdlib.all;library gaisler;use gaisler.libdcom.all;use gaisler.sim.all;use gaisler.jtagtst.all;library techmap;use techmap.gencomp.all;library micron;use micron.components.all;use work.debug.all;use work.config.all;	-- configurationentity testbench is  generic (    fabtech   : integer := CFG_FABTECH;    memtech   : integer := CFG_MEMTECH;    padtech   : integer := CFG_PADTECH;    clktech   : integer := CFG_CLKTECH;    ncpu      : integer := CFG_NCPU;    disas     : integer := CFG_DISAS;	-- Enable disassembly to console    dbguart   : integer := CFG_DUART;	-- Print UART on console    pclow     : integer := CFG_PCLOW;    clkperiod : integer := 20;		-- system clock period    romwidth  : integer := 32;		-- rom data width (8/32)    romdepth  : integer := 16;		-- rom address depth    sramwidth  : integer := 32;		-- ram data width (8/16/32)    sramdepth  : integer := 17;		-- ram address depth    srambanks  : integer := 2		-- number of ram banks  );  port (    pci_rst     : in std_ulogic;	-- PCI bus    pci_clk 	: in std_ulogic;    pci_gnt     : in std_ulogic;    pci_idsel   : in std_ulogic;    pci_lock    : inout std_ulogic;    pci_ad 	: inout std_logic_vector(31 downto 0);    pci_cbe 	: inout std_logic_vector(3 downto 0);    pci_frame   : inout std_ulogic;    pci_irdy 	: inout std_ulogic;    pci_trdy 	: inout std_ulogic;    pci_devsel  : inout std_ulogic;    pci_stop 	: inout std_ulogic;    pci_perr 	: inout std_ulogic;    pci_par 	: inout std_ulogic;    pci_req 	: inout std_ulogic;    pci_serr    : inout std_ulogic;    pci_host   	: in std_ulogic;    pci_66	: in std_ulogic  );end;architecture behav of testbench isconstant promfile  : string := "prom.srec";  -- rom contentsconstant sramfile  : string := "sram.srec";  -- ram contentsconstant sdramfile : string := "sdram.srec"; -- sdram contentscomponent leon3mp  generic (    fabtech  : integer := CFG_FABTECH;    memtech  : integer := CFG_MEMTECH;    padtech  : integer := CFG_PADTECH;    clktech  : integer := CFG_CLKTECH;    disas     : integer := CFG_DISAS;	-- Enable disassembly to console    dbguart   : integer := CFG_DUART;	-- Print UART on console    pclow     : integer := CFG_PCLOW  );  port (    resetn	: in  std_ulogic;    clk		: in  std_ulogic;    pllref 	: in  std_ulogic;    errorn	: out std_ulogic;    address 	: out std_logic_vector(27 downto 0);    data	: inout std_logic_vector(31 downto 0);    sa      	: out std_logic_vector(14 downto 0);    sd   	: inout std_logic_vector(63 downto 0);    sdclk  	: out std_ulogic;    sdcke  	: out std_logic_vector (1 downto 0);    -- sdram clock enable    sdcsn  	: out std_logic_vector (1 downto 0);    -- sdram chip select    sdwen  	: out std_ulogic;                       -- sdram write enable    sdrasn  	: out std_ulogic;                       -- sdram ras    sdcasn  	: out std_ulogic;                       -- sdram cas    sddqm   	: out std_logic_vector (7 downto 0);    -- sdram dqm    dsutx  	: out std_ulogic; 			-- DSU tx data    dsurx  	: in  std_ulogic;  			-- DSU rx data    dsuen   	: in std_ulogic;    dsubre  	: in std_ulogic;    dsuact  	: out std_ulogic;    txd1   	: out std_ulogic; 			-- UART1 tx data    rxd1   	: in  std_ulogic;  			-- UART1 rx data    txd2   	: out std_ulogic; 			-- UART1 tx data    rxd2   	: in  std_ulogic;  			-- UART1 rx data    ramsn  	: out std_logic_vector (4 downto 0);    ramoen 	: out std_logic_vector (4 downto 0);    rwen   	: out std_logic_vector (3 downto 0);    oen    	: out std_ulogic;    writen 	: out std_ulogic;    read   	: out std_ulogic;    iosn   	: out std_ulogic;    romsn  	: out std_logic_vector (1 downto 0);    gpio        : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); 	-- I/O port    emdio     	: inout std_logic;		-- ethernet PHY interface    etx_clk 	: in std_logic;    erx_clk 	: in std_logic;    erxd    	: in std_logic_vector(3 downto 0);    erx_dv  	: in std_logic;    erx_er  	: in std_logic;    erx_col 	: in std_logic;    erx_crs 	: in std_logic;    etxd 	: out std_logic_vector(3 downto 0);    etx_en 	: out std_logic;    etx_er 	: out std_logic;    emdc 	: out std_logic;    emddis 	: out std_logic;    epwrdwn 	: out std_logic;    ereset 	: out std_logic;    esleep 	: out std_logic;    epause 	: out std_logic;    pci_rst     : in std_ulogic;		-- PCI bus    pci_clk 	: in std_ulogic;    pci_gnt     : in std_ulogic;    pci_idsel   : in std_ulogic;    pci_lock    : inout std_ulogic;    pci_ad 	: inout std_logic_vector(31 downto 0);    pci_cbe 	: inout std_logic_vector(3 downto 0);    pci_frame   : inout std_ulogic;    pci_irdy 	: inout std_ulogic;    pci_trdy 	: inout std_ulogic;    pci_devsel  : inout std_ulogic;    pci_stop 	: inout std_ulogic;    pci_perr 	: inout std_ulogic;    pci_par 	: inout std_ulogic;    pci_req 	: inout std_ulogic;    pci_serr    : inout std_ulogic;    pci_host   	: in std_ulogic;    pci_66	: in std_ulogic;    pci_arb_req	: in  std_logic_vector(0 to 3);    pci_arb_gnt	: out std_logic_vector(0 to 3);    can_txd	: out std_ulogic;    can_rxd	: in  std_ulogic;    can_stb	: out std_ulogic;    spw_clk	: in  std_ulogic;    spw_rxd     : in  std_logic_vector(0 to 2);    spw_rxdn    : in  std_logic_vector(0 to 2);    spw_rxs     : in  std_logic_vector(0 to 2);    spw_rxsn    : in  std_logic_vector(0 to 2);    spw_txd     : out std_logic_vector(0 to 2);    spw_txdn    : out std_logic_vector(0 to 2);    spw_txs     : out std_logic_vector(0 to 2);    spw_txsn    : out std_logic_vector(0 to 2);    tck, tms, tdi : in std_ulogic;    tdo         : out std_ulogic	);end component;signal clk : std_logic := '0';signal Rst    : std_logic := '0';			-- Resetconstant ct : integer := clkperiod/2;signal address  : std_logic_vector(27 downto 0);signal data     : std_logic_vector(31 downto 0);signal ramsn    : std_logic_vector(4 downto 0);signal ramoen   : std_logic_vector(4 downto 0);signal rwen     : std_logic_vector(3 downto 0);signal rwenx    : std_logic_vector(3 downto 0);signal romsn    : std_logic_vector(1 downto 0);signal iosn     : std_ulogic;signal oen      : std_ulogic;signal read     : std_ulogic;signal writen   : std_ulogic;signal brdyn    : std_ulogic;signal bexcn    : std_ulogic;signal wdog     : std_ulogic;signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;signal dsurst   : std_ulogic;signal test     : std_ulogic;signal error    : std_logic;signal gpio	: std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);signal GND      : std_ulogic := '0';signal VCC      : std_ulogic := '1';signal NC       : std_ulogic := 'Z';signal clk2     : std_ulogic := '1';signal sdcke    : std_logic_vector ( 1 downto 0);  -- clk ensignal sdcsn    : std_logic_vector ( 1 downto 0);  -- chip selsignal sdwen    : std_ulogic;                       -- write ensignal sdrasn   : std_ulogic;                       -- row addr stbsignal sdcasn   : std_ulogic;                       -- col addr stbsignal sddqm    : std_logic_vector ( 7 downto 0);  -- data i/o masksignal sdclk    : std_ulogic;signal plllock    : std_ulogic;signal txd1, rxd1 : std_ulogic;signal txd2, rxd2 : std_ulogic;signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not usedsignal emddis 	: std_logic;signal epwrdwn 	: std_logic;signal ereset 	: std_logic;signal esleep 	: std_logic;signal epause 	: std_logic;signal led_cfg: std_logic_vector(2 downto 0);constant lresp : boolean := false;signal sa      	: std_logic_vector(14 downto 0);signal sd   	: std_logic_vector(63 downto 0);signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);signal can_txd	: std_ulogic;signal can_rxd	: std_ulogic;signal can_stb	: std_ulogic;signal spw_clk	: std_ulogic := '0';signal spw_rxd  : std_logic_vector(0 to 2) := "000";signal spw_rxdn : std_logic_vector(0 to 2) := "000";signal spw_rxs  : std_logic_vector(0 to 2) := "000";signal spw_rxsn : std_logic_vector(0 to 2) := "000";signal spw_txd  : std_logic_vector(0 to 2);signal spw_txdn : std_logic_vector(0 to 2);signal spw_txs  : std_logic_vector(0 to 2);signal spw_txsn : std_logic_vector(0 to 2);signal tck, tms, tdi, tdo : std_ulogic;constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;