Release 7.1.04i - xst H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 2.29 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 2.29 s | Elapsed : 0.00 / 1.00 s --> Reading design: lcd.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "lcd.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "lcd"Output Format                      : NGCTarget Device                      : xc3s400-4-pq208---- Source OptionsTop Module Name                    : lcdAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : lcd.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/LCD/char_ram.vhd" in Library work.Architecture fun of Entity char_ram is up to date.Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/LCD/lcd.vhd" in Library work.Entity <lcd> compiled.Entity <lcd> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <lcd> (Architecture <behavioral>).INFO:Xst:1739 - HDL ADVISOR - "E:/Cindy/working/UE_EXTBOARD/LCD/lcd.vhd" line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.Entity <lcd> analyzed. Unit <lcd> generated.Analyzing Entity <char_ram> (Architecture <fun>).Entity <char_ram> analyzed. Unit <char_ram> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <char_ram>.    Related source file is "E:/Cindy/working/UE_EXTBOARD/LCD/char_ram.vhd".    Found 32x8-bit ROM for signal <$n0000>.    Summary:	inferred   1 ROM(s).Unit <char_ram> synthesized.Synthesizing Unit <lcd>.    Related source file is "E:/Cindy/working/UE_EXTBOARD/LCD/lcd.vhd".    Using one-hot encoding for signal <state>.    Found 1-bit register for signal <lcd_e>.    Found 8-bit tristate buffer for signal <data>.    Found 4-bit comparator less for signal <$n0007> created at line 167.    Found 7-bit comparator less for signal <$n0009> created at line 196.    Found 4-bit 4-to-1 multiplexer for signal <$n0026>.    Found 6-bit adder for signal <$n0027>.    Found 6-bit subtractor for signal <$n0028>.    Found 7-bit adder for signal <$n0031> created at line 199.    Found 4-bit adder for signal <$n0032> created at line 168.    Found 7-bit comparator less for signal <$n0039> created at line 144.    Found 7-bit comparator greater for signal <$n0040> created at line 144.    Found 7-bit comparator less for signal <$n0041> created at line 144.    Found 7-bit comparator greater for signal <$n0042> created at line 144.    Found 1-bit register for signal <clk_int>.    Found 21-bit up counter for signal <clkcnt>.    Found 1-bit register for signal <clkdiv>.    Found 7-bit register for signal <counter>.    Found 4-bit register for signal <div_counter>.    Found 1-bit register for signal <flag>.    Found 11-bit register for signal <state>.    Summary:	inferred   1 Counter(s).	inferred  15 D-type flip-flop(s).	inferred   4 Adder/Subtractor(s).	inferred   6 Comparator(s).	inferred   4 Multiplexer(s).	inferred   8 Tristate(s).Unit <lcd> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs                             : 1 32x8-bit ROM                      : 1# Adders/Subtractors               : 4 4-bit adder                       : 1 6-bit adder                       : 1 6-bit subtractor                  : 1 7-bit adder                       : 1# Counters                         : 1 21-bit up counter                 : 1# Registers                        : 7 1-bit register                    : 4 11-bit register                   : 1 4-bit register                    : 1 7-bit register                    : 1# Comparators                      : 6 4-bit comparator less             : 1 7-bit comparator greater          : 2 7-bit comparator less             : 3# Multiplexers                     : 1 4-bit 4-to-1 multiplexer          : 1# Tristates                        : 1 8-bit tristate buffer             : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1710 - FF/Latch  <state_10> (without init value) has a constant value of 0 in block <lcd>.WARNING:Xst:1710 - FF/Latch  <state_2> (without init value) has a constant value of 0 in block <lcd>.WARNING:Xst:1710 - FF/Latch  <state_7> (without init value) has a constant value of 0 in block <lcd>.Optimizing unit <lcd> ...Optimizing unit <char_ram> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block lcd, actual ratio is 2.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : lcd.ngrTop Level Output File Name         : lcdOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 13Macro Statistics :# ROMs                             : 1#      32x8-bit ROM                : 1# Registers                        : 17#      1-bit register              : 15#      4-bit register              : 1#      7-bit register              : 1# Counters                         : 1#      21-bit up counter           : 1# Multiplexers                     : 1#      4-bit 4-to-1 multiplexer    : 1# Tristates                        : 1#      8-bit tristate buffer       : 1# Adders/Subtractors               : 2#      6-bit subtractor            : 1#      7-bit adder                 : 1# Comparators                      : 6#      4-bit comparator less       : 1#      7-bit comparator greater    : 2#      7-bit comparator less       : 3Cell Usage :# BELS                             : 212#      GND                         : 1#      INV                         : 7#      LUT1                        : 7#      LUT1_L                      : 5#      LUT2                        : 12#      LUT2_L                      : 4