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Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/LCD/char_ram.vhd" in Library work.Architecture fun of Entity char_ram is up to date.Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/LCD/lcd.vhd" in Library work.Entity <lcd> compiled.Entity <lcd> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <lcd> (Architecture <behavioral>).INFO:Xst:1739 - HDL ADVISOR - "E:/Cindy/working/UE_EXTBOARD/LCD/lcd.vhd" line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.Entity <lcd> analyzed. Unit <lcd> generated.Analyzing Entity <char_ram> (Architecture <fun>).Entity <char_ram> analyzed. Unit <char_ram> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <char_ram>.    Related source file is "E:/Cindy/working/UE_EXTBOARD/LCD/char_ram.vhd".    Found 32x8-bit ROM for signal <$n0000>.    Summary:	inferred   1 ROM(s).Unit <char_ram> synthesized.Synthesizing Unit <lcd>.    Related source file is "E:/Cindy/working/UE_EXTBOARD/LCD/lcd.vhd".    Using one-hot encoding for signal <state>.    Found 1-bit register for signal <lcd_e>.    Found 8-bit tristate buffer for signal <data>.    Found 4-bit comparator less for signal <$n0007> created at line 167.    Found 7-bit comparator less for signal <$n0009> created at line 196.    Found 4-bit 4-to-1 multiplexer for signal <$n0026>.    Found 6-bit adder for signal <$n0027>.    Found 6-bit subtractor for signal <$n0028>.    Found 7-bit adder for signal <$n0031> created at line 199.    Found 4-bit adder for signal <$n0032> created at line 168.    Found 7-bit comparator less for signal <$n0039> created at line 144.    Found 7-bit comparator greater for signal <$n0040> created at line 144.    Found 7-bit comparator less for signal <$n0041> created at line 144.    Found 7-bit comparator greater for signal <$n0042> created at line 144.    Found 1-bit register for signal <clk_int>.    Found 21-bit up counter for signal <clkcnt>.    Found 1-bit register for signal <clkdiv>.    Found 7-bit register for signal <counter>.    Found 4-bit register for signal <div_counter>.    Found 1-bit register for signal <flag>.    Found 11-bit register for signal <state>.    Summary:	inferred   1 Counter(s).	inferred  15 D-type flip-flop(s).	inferred   4 Adder/Subtractor(s).	inferred   6 Comparator(s).	inferred   4 Multiplexer(s).	inferred   8 Tristate(s).Unit <lcd> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs                             : 1 32x8-bit ROM                      : 1# Adders/Subtractors               : 4 4-bit adder                       : 1 6-bit adder                       : 1 6-bit subtractor                  : 1 7-bit adder                       : 1# Counters                         : 1 21-bit up counter                 : 1# Registers                        : 7 1-bit register                    : 4 11-bit register                   : 1 4-bit register                    : 1 7-bit register                    : 1# Comparators                      : 6 4-bit comparator less             : 1 7-bit comparator greater          : 2 7-bit comparator less             : 3# Multiplexers                     : 1 4-bit 4-to-1 multiplexer          : 1# Tristates                        : 1 8-bit tristate buffer             : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1710 - FF/Latch  <state_10> (without init value) has a constant value of 0 in block <lcd>.WARNING:Xst:1710 - FF/Latch  <state_2> (without init value) has a constant value of 0 in block <lcd>.WARNING:Xst:1710 - FF/Latch  <state_7> (without init value) has a constant value of 0 in block <lcd>.Optimizing unit <lcd> ...Optimizing unit <char_ram> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block lcd, actual ratio is 2.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4  Number of Slices:                      72  out of   3584     2%   Number of Slice Flip Flops:            44  out of   7168     0%   Number of 4 input LUTs:               128  out of   7168     1%   Number of bonded IOBs:                 13  out of    141     9%   Number of GCLKs:                        2  out of      8    25%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 21    |clk_int:Q                          | BUFG                   | 20    |tc_clkcnt(_n0020103:O)             | NONE(*)(clkdiv)        | 1     |clkdiv:Q                           | NONE                   | 2     |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -4   Minimum period: 8.987ns (Maximum Frequency: 111.272MHz)   Minimum input arrival time before clock: No path found   Maximum output required time after clock: 23.389ns   Maximum combinational path delay: No path found=========================================================================
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\cindy\working\ue_extboard\lcd/_ngo-nt timestamp -uc LCD.ucf -p xc3s400-pq208-4 lcd.ngc lcd.ngd Reading NGO file 'E:/Cindy/working/UE_EXTBOARD/LCD/lcd.ngc' ...Applying constraints in "LCD.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "lcd.ngd" ...Writing NGDBUILD log file "lcd.bld"...NGDBUILD done.
Started process "Map".Using target part "3s400pq208-4".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors:      0Number of warnings:    2Logic Utilization:  Number of Slice Flip Flops:          44 out of   7,168    1%  Number of 4 input LUTs:             119 out of   7,168    1%Logic Distribution:  Number of occupied Slices:                           73 out of   3,584    2%    Number of Slices containing only related logic:      73 out of      73  100%    Number of Slices containing unrelated logic:          0 out of      73    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:            131 out of   7,168    1%  Number used as logic:                119  Number used as a route-thru:          12  Number of bonded IOBs:               13 out of     141    9%  Number of GCLKs:                     2 out of       8   25%Total equivalent gate count for design:  1,321Additional JTAG gate count for IOBs:  624Peak Memory Usage:  102 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Mapping completed.See MAP report file "lcd_map.mrp" for details.
Started process "Place & Route".Constraints file: lcd.pcf.Loading device for application Rf_Device from file '3s400.nph' in environmentD:/Xilinx.   "lcd" is an NCD, version 3.1, device xc3s400, package pq208, speed -4Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)Device speed data version:  "PRODUCTION 1.37 2005-07-22".Device Utilization Summary:   Number of BUFGMUXs                  2 out of 8      25%   Number of External IOBs            13 out of 141     9%      Number of LOCed IOBs            13 out of 13    100%   Number of Slices                   73 out of 3584    2%      Number of SLICEMs                0 out of 1792    0%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Starting PlacerPhase 1.1Phase 1.1 (Checksum:989835) REAL time: 2 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs Phase 3.2.Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs Phase 4.8.Phase 4.8 (Checksum:994647) REAL time: 2 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs Phase 6.18Phase 6.18 (Checksum:39386fa) REAL time: 2 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs Writing design to file lcd.ncdTotal REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 1 secs Starting RouterPhase 1: 549 unrouted;       REAL time: 2 secs Phase 2: 517 unrouted;       REAL time: 2 secs Phase 3: 221 unrouted;       REAL time: 2 secs Phase 4: 0 unrouted;       REAL time: 2 secs WARNING:Route - CLK Net:clkdivmay have excessive skew because 1 NON-CLK pinsfailed to route using a CLK template.WARNING:Route - CLK Net:clk_intmay have excessive skew because 1 NON-CLK pinsfailed to route using a CLK template.Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|           clk_BUFGP |      BUFGMUX1| No   |   11 |  0.019     |  1.033      |+---------------------+--------------+------+------+------------+-------------+|             clk_int |      BUFGMUX6| No   |   15 |  0.020     |  1.034      |+---------------------+--------------+------+------+------------+-------------+|           tc_clkcnt |         Local|      |    1 |  0.000     |  1.010      |+---------------------+--------------+------+------+------------+-------------+|              clkdiv |         Local|      |    3 |  0.065     |  2.049      |+---------------------+--------------+------+------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 3 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage:  77 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 2Number of info messages: 1Writing design to file lcd.ncdPAR done!Started process "Generate Post-Place & Route Static Timing".Loading device for application Rf_Device from file '3s400.nph' in environmentD:/Xilinx.   "lcd" is an NCD, version 3.1, device xc3s400, package pq208, speed -4Analysis completed Tue Feb 07 14:09:41 2006--------------------------------------------------------------------------------Generating Report ...Number of warnings: 0Total time: 2 secs 

Started process "Generate Programming File".WARNING:PhysDesignRules:372 - Gated clock. Clock net tc_clkcnt is sourced by a   combinatorial pin. This is not good design practice. Use the CE pin to   control the loading of data into the flip-flop.

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