-- VHDL Instantiation Created from source file mdecode.vhd -- 15:17:03 04/05/2006
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT mdecode
	PORT(
		CS_MC : IN std_logic;
		MADDR1 : IN std_logic;
		MADDR2 : IN std_logic;
		MA0 : IN std_logic;
		MB0 : IN std_logic;
		MC0 : IN std_logic;
		RD : IN std_logic;          
		NEGM : OUT std_logic;
		O : OUT std_logic_vector(7 downto 0);
		POSM : OUT std_logic
		);
	END COMPONENT;

	Inst_mdecode: mdecode PORT MAP(
		CS_MC => ,
		MADDR1 => ,
		MADDR2 => ,
		MA0 => ,
		MB0 => ,
		MC0 => ,
		RD => ,
		NEGM => ,
		O => ,
		POSM => 
	);