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?? fir_top.qsf

?? logic lock 的vhdl源碼
?? QSF
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set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y3 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_memory_reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y3 -to "fir_top_st:fir_top_st_component\|scale_accum:Usa\|accum\[12\]~COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y3 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_address_reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y3 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_address_reg1" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y3 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~porta_address_reg2" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y3 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~portb_address_reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y3 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~portb_address_reg1" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y3 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur2_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_6m41:auto_generated\|ram_block1a0~portb_address_reg2" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[1\]~reg0COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y3 -to "fir_top_st:fir_top_st_component\|scale_accum:Usa\|rst_dly" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[6\]~reg0COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[11\]~reg0COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[13\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[12\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[11\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[10\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[1\]~reg0COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[9\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[8\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[7\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[6\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[5\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[4\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[3\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[2\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[1\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[0\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[6\]~reg0COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X13_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_1_n_0_n\|res\[14\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[12\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[10\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[9\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X7_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[8\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_we_reg" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_re_reg" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[7\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_datain_reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_memory_reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[11\]~reg0COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[6\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg1" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[5\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg2" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg3" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y4 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[4\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg4" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg5" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[3\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg6" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~porta_address_reg7" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[2\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg1" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X12_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[1\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg2" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg3" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_1_n\|res\[0\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg4" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg5" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg6" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION M4K_X15_Y1 -to "fir_top_st:fir_top_st_component\|ram_lut:Ur1_n\|ram_2pt_var:ram\|altsyncram:altsyncram_component\|altsyncram_rs41:auto_generated\|ram_block1a0~portb_address_reg7" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[12\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[11\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y4 -to "fir_top_st:fir_top_st_component\|scale_accum:Usa\|a_inv_mx\[1\]~COUT" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[10\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[9\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[8\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y1 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[7\]~reg0" -section_id fir_lock
set_instance_assignment -name LL_NODE_LOCATION LAB_X14_Y2 -to "fir_top_st:fir_top_st_component\|sadd:Uaddl_0_n_0_n\|res\[6\]~reg0" -section_id fir_lock

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亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频
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