?? cpld_for_lcd.tan.rpt
字號:
Timing Analyzer report for cpld_for_lcd
Tue May 29 16:51:26 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-----------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------+--------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 17.700 ns ; MSTR_nRST ; RED[1] ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-----------+--------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM3128ATC100-10 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+-----------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+-----------+----------+
; N/A ; None ; 17.700 ns ; MSTR_nRST ; BLUE[2] ;
; N/A ; None ; 17.700 ns ; MSTR_nRST ; BLUE[1] ;
; N/A ; None ; 17.700 ns ; MSTR_nRST ; BLUE[0] ;
; N/A ; None ; 17.700 ns ; MSTR_nRST ; GREEN[2] ;
; N/A ; None ; 17.700 ns ; MSTR_nRST ; GREEN[1] ;
; N/A ; None ; 17.700 ns ; MSTR_nRST ; GREEN[0] ;
; N/A ; None ; 17.700 ns ; MSTR_nRST ; RED[2] ;
; N/A ; None ; 17.700 ns ; MSTR_nRST ; RED[1] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; BLUE[2] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; BLUE[1] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; BLUE[0] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; GREEN[2] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; GREEN[1] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; GREEN[0] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; RED[2] ;
; N/A ; None ; 17.300 ns ; LCD_D[15] ; RED[1] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; DE ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; HS ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; VS ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; BLUE[7] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; BLUE[6] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; BLUE[5] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; BLUE[4] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; BLUE[3] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; GREEN[7] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; GREEN[6] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; GREEN[5] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; GREEN[4] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; GREEN[3] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; RED[7] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; RED[6] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; RED[5] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; RED[4] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; RED[3] ;
; N/A ; None ; 10.400 ns ; MSTR_nRST ; RED[0] ;
; N/A ; None ; 10.000 ns ; LCD_MDISP ; DE ;
; N/A ; None ; 10.000 ns ; LCD_HSYNC ; HS ;
; N/A ; None ; 10.000 ns ; LCD_VSYNC ; VS ;
; N/A ; None ; 10.000 ns ; LCD_D[14] ; BLUE[7] ;
; N/A ; None ; 10.000 ns ; LCD_D[13] ; BLUE[6] ;
; N/A ; None ; 10.000 ns ; LCD_D[12] ; BLUE[5] ;
; N/A ; None ; 10.000 ns ; LCD_D[11] ; BLUE[4] ;
; N/A ; None ; 10.000 ns ; LCD_D[10] ; BLUE[3] ;
; N/A ; None ; 10.000 ns ; LCD_D[9] ; GREEN[7] ;
; N/A ; None ; 10.000 ns ; LCD_D[8] ; GREEN[6] ;
; N/A ; None ; 10.000 ns ; LCD_D[7] ; GREEN[5] ;
; N/A ; None ; 10.000 ns ; LCD_D[6] ; GREEN[4] ;
; N/A ; None ; 10.000 ns ; LCD_D[5] ; GREEN[3] ;
; N/A ; None ; 10.000 ns ; LCD_D[4] ; RED[7] ;
; N/A ; None ; 10.000 ns ; LCD_D[3] ; RED[6] ;
; N/A ; None ; 10.000 ns ; LCD_D[2] ; RED[5] ;
; N/A ; None ; 10.000 ns ; LCD_D[1] ; RED[4] ;
; N/A ; None ; 10.000 ns ; LCD_D[0] ; RED[3] ;
; N/A ; None ; 10.000 ns ; LCD_D[15] ; RED[0] ;
+-------+-------------------+-----------------+-----------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Tue May 29 16:51:25 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cpld_for_lcd -c cpld_for_lcd
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
Info: Node "DE$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "HS$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "VS$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "BLUE[7]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "BLUE[6]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "BLUE[5]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "BLUE[4]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "BLUE[3]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "GREEN[7]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "GREEN[6]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "GREEN[5]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "GREEN[4]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "GREEN[3]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "RED[7]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "RED[6]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "RED[5]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "RED[4]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "RED[3]$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "RED[0]$latch~26"
Info: Longest tpd from source pin "MSTR_nRST" to destination pin "BLUE[2]" is 17.700 ns
Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 57; PIN Node = 'MSTR_nRST'
Info: 2: + IC(0.000 ns) + CELL(6.300 ns) = 8.800 ns; Loc. = LC33; Fanout = 11; COMB LOOP Node = 'RED[0]$latch~26'
Info: Loc. = LC33; Node "RED[0]$latch~26"
Info: 3: + IC(2.900 ns) + CELL(4.400 ns) = 16.100 ns; Loc. = LC102; Fanout = 1; COMB Node = 'RED[0]$latch~28'
Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 17.700 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'BLUE[2]'
Info: Total cell delay = 14.800 ns ( 83.62 % )
Info: Total interconnect delay = 2.900 ns ( 16.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue May 29 16:51:26 2007
Info: Elapsed time: 00:00:01
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