{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 29 16:51:17 2007 " "Info: Processing started: Tue May 29 16:51:17 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpld_for_lcd -c cpld_for_lcd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpld_for_lcd -c cpld_for_lcd" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld_for_lcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpld_for_lcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpld_for_lcd " "Info: Found entity 1: cpld_for_lcd" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cpld_for_lcd " "Info: Elaborating entity \"cpld_for_lcd\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "VS_BUF cpld_for_lcd.v(58) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(58): variable \"VS_BUF\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 58 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "HS_BUF cpld_for_lcd.v(59) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(59): variable \"HS_BUF\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "DE_BUF cpld_for_lcd.v(60) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(60): variable \"DE_BUF\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 60 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "VS cpld_for_lcd.v(48) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable \"VS\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"VS\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "HS cpld_for_lcd.v(48) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable \"HS\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"HS\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "DE cpld_for_lcd.v(48) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable \"DE\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"DE\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "BLUE cpld_for_lcd.v(48) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable \"BLUE\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"BLUE\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "GREEN cpld_for_lcd.v(48) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable \"GREEN\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"GREEN\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "RED cpld_for_lcd.v(48) " "Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable \"RED\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"RED\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 48 0 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "19 " "Info: Ignored 19 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "19 " "Info: Ignored 19 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IOPT_MLS_DUP_LATCH_INFO" "BLUE\[2\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"BLUE\[2\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "BLUE\[1\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"BLUE\[1\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "BLUE\[0\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"BLUE\[0\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "GREEN\[2\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"GREEN\[2\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "GREEN\[1\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"GREEN\[1\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "GREEN\[0\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"GREEN\[0\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "RED\[2\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"RED\[2\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "RED\[1\]\$latch RED\[0\]\$latch " "Info: Duplicate LATCH primitive \"RED\[1\]\$latch\" merged with LATCH primitive \"RED\[0\]\$latch\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "13 " "Warning: Design contains 13 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "BUFFERED_CLOCK " "Warning: No output dependent on input pin \"BUFFERED_CLOCK\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 12 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_TYPE\[0\] " "Warning: No output dependent on input pin \"LCD_TYPE\[0\]\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 13 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_TYPE\[1\] " "Warning: No output dependent on input pin \"LCD_TYPE\[1\]\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 13 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_TYPE\[2\] " "Warning: No output dependent on input pin \"LCD_TYPE\[2\]\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 13 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_DON " "Warning: No output dependent on input pin \"LCD_DON\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 11 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_REV " "Warning: No output dependent on input pin \"LCD_REV\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 11 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_CLS " "Warning: No output dependent on input pin \"LCD_CLS\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 11 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_PSAVE " "Warning: No output dependent on input pin \"LCD_PSAVE\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 11 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "uP_PC6 " "Warning: No output dependent on input pin \"uP_PC6\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 14 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_MOD " "Warning: No output dependent on input pin \"LCD_MOD\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 11 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_SPL " "Warning: No output dependent on input pin \"LCD_SPL\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 10 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_D\[16\] " "Warning: No output dependent on input pin \"LCD_D\[16\]\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 9 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LCD_D\[17\] " "Warning: No output dependent on input pin \"LCD_D\[17\]\"" {  } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "87 " "Info: Implemented 87 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "33 " "Info: Implemented 33 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "27 " "Info: Implemented 27 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "27 " "Info: Implemented 27 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 23 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 29 16:51:18 2007 " "Info: Processing ended: Tue May 29 16:51:18 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}