?? sfrs.c
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/***************************************************************************
* This code and information is provided "as is" without warranty of any *
* kind, either expressed or implied, including but not limited to the *
* implied warranties of merchantability and/or fitness for a particular *
* purpose. *
* *
* Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved. *
***************************************************************************/
//**************************************************************************
// DESCRIPTION: 71M652x POWER METER - Special Function Register Access.
//
// AUTHOR: MTF
//
// HISTORY: See end of file
//**************************************************************************
// File: SFRS.C
//
// Low level API for SFRs and MEMORY.
//
#include "options.h"
#include "sfrs.h" // included to assure interface is right
/*** External functions used within this module ***/
// None.
/*** External variables used within this module ***/
// None.
/*** Public functions declared within this module ***/
// see sfrs.h
/*** Public variables declared within this module ***/
// None.
/*** Private functions declared within this module ***/
// None.
/*** Private variables declared within this module ***/
// None.
// SFR API
//
#pragma save
#pragma NOAREGS
enum SFR_RC SFR_Read (uint8_t s, int8d_t *pc) small reentrant
{
enum SFR_RC rc = SFR_OK;
int8_t c;
switch (s | 0x80)
{ //
case 0x80: c = P0; break; //
case 0x81: c = SP; break; //
case 0x82: c = DPL; break; //
case 0x83: c = DPH; break; //
case 0x84: c = DPL1; break; //
case 0x85: c = DPH1; break; //
case 0x86: c = WDTREL; break; //
case 0x87: c = PCON; break; //
case 0x88: c = TCON; break; //
case 0x89: c = TMOD; break; //
case 0x8A: c = TL0; break; //
case 0x8B: c = TL1; break; //
case 0x8C: c = TH0; break; //
case 0x8D: c = TH1; break; //
case 0x8E: c = CKCON; break; //
case 0x90: c = P1; break; //
case 0x91: c = DIR1; break; //
case 0x92: c = DPS; break; //
case 0x94: c = ERASE; break; //
case 0x98: c = SCON; break; //
case 0x99: c = SBUF; break; //
case 0x9A: c = IEN2; break; //
case 0x9B: c = S1CON; break; //
case 0x9C: c = S1BUF; break; //
case 0x9D: c = S1RELL; break; //
case 0x9E: c = EEDATA; break; //
case 0x9F: c = EECTRL; break; //
case 0xA0: c = P2; break; //
case 0xA1: c = DIR2; break; //
case 0xA2: c = DIR0; break; //
case 0xA8: c = IE; break; //
case 0xA9: c = IP; break; //
case 0xAA: c = S0RELL; break; //
case 0xB0: c = P3; break; //
case 0xB2: c = FCTRL; break; //
case 0xB7: c = FPAGE; break; //
case 0xB8: c = IEN1; break; //
case 0xB9: c = IP1; break; //
case 0xBA: c = S0RELH; break; //
case 0xBB: c = S1RELH; break; //
case 0xBF: c = ADRMSB; break; //
case 0xC0: c = IRCON; break; //
case 0xC8: c = T2CON; break; //
case 0xD0: c = PSW; break; //
case 0xD8: c = WDCON; break; //
case 0xE8: c = IFLAGS; break; //
case 0xF0: c = B; break; //
case 0xF8: c = INTBIT; break; //
default:
rc = SFR_INVALID;
c = 0xff;
break;
}
*pc = c;
return (rc);
}
#pragma restore
#pragma save
#pragma NOAREGS
enum SFR_RC SFR_Write (uint8_t s, uint8_t c, uint8_t op) small reentrant
{
static enum SFR_RC rc;
static uint8_t data d;
switch (op)
{
case ASSIGN:
rc = SFR_OK;
break;
case AND:
if (rc = SFR_Read (s, (int8d_t *) &d) != SFR_OK)
return (rc);
c &= d;
break;
case OR:
if (rc = SFR_Read (s, (int8d_t *) &d) != SFR_OK)
return (rc);
c |= d;
break;
}
switch (s | 0x80)
{ //
case 0x80: P0 = c; break; //
case 0x81: SP = c; break; //
case 0x82: DPL = c; break; //
case 0x83: DPH = c; break; //
case 0x84: DPL1 = c; break; //
case 0x85: DPH1 = c; break; //
case 0x86: WDTREL = c; break; //
case 0x87: PCON = c; break; //
case 0x88: TCON = c; break; //
case 0x89: TMOD = c; break; //
case 0x8A: TL0 = c; break; //
case 0x8B: TL1 = c; break; //
case 0x8C: TH0 = c; break; //
case 0x8D: TH1 = c; break; //
case 0x8E: CKCON = c; break; //
case 0x90: USER1 = c; break; //
case 0x91: DIR1 = c; break; //
case 0x92: DPS = c; break; //
case 0x94: ERASE = c; break; //
case 0x98: SCON = c; break; //
case 0x99: SBUF = c; break; //
case 0x9A: IEN2 = c; break; //
case 0x9B: S1CON = c; break; //
case 0x9C: S1BUF = c; break; //
case 0x9D: S1RELL = c; break; //
case 0x9E: EEDATA = c; break; //
case 0x9F: EECTRL = c; break; //
case 0xA0: P2 = c; break; //
case 0xA1: DIR2 = c; break; //
case 0xA2: DIR0 = c; break; //
case 0xA8: IE = c; break; //
case 0xA9: IP = c; break; //
case 0xAA: S0RELL = c; break; //
case 0xB0: P3 = c; break; //
case 0xB2: EA = FALSE; FCTRL = c; EA = TRUE; break;
case 0xB7: EA = FALSE; FPAGE = c; EA = TRUE; break;
case 0xB8: IEN1 = c; break; //
case 0xB9: IP1 = c; break; //
case 0xBA: S0RELH = c; break; //
case 0xBB: S1RELH = c; break; //
case 0xBF: ADRMSB = c; break; //
case 0xC0: IRCON = c; break; //
case 0xC8: T2CON = c; break; //
case 0xD0: PSW = c; break; //
case 0xD8: WDCON = c; break; //
case 0xE8: IFLAGS = c; break; //
case 0xF0: B = c; break; //
case 0xF8: INTBIT = c; break; //
default:
break;
}
return (rc);
}
#pragma restore
/***************************************************************************
* History:
* $Log: sfrs.c,v $
* Revision 1.5 2006/09/09 01:15:55 gmikef
* *** empty log message ***
*
* Revision 1.4 2006/06/29 00:58:44 tvander
* Added NOAREGs to reentrant code.
*
* Revision 1.2 2005/09/22 23:45:29 tvander
* Clean build all models and unit tests, updated copyright to be fore Teridian
*
* Revision 1.1 2005/08/22 22:30:57 tvander
* Clean build of FLAG system
* No pulse counting.
* No debug/CLI.
*
* Revision 1.1 2005/08/18 02:56:09 gmikef
* *** empty log message ***
*
* Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved. *
* this program is fully protected by the United States copyright *
* laws and is the property of Teridian Semiconductor Corporation. *
***************************************************************************/
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