sfr FCTRL = 0xB2;                       // Flash Control.
#define PREBOOT_   BIT7                 // In 'preboot' state, ICE locked out.
#define SECURE_    BIT6                 // In 'secure' mode, reading of FLASH prohibited.
//.....................
#define MEEN_      BIT1                 // Mass Erase enable, auto-clears.
#define PWE_       BIT0                 // Program Write Enable, MOVX @DPTR,A writes to code space (Flash).

sfr FPAGE = 0xB7;                       // Flash Page Erase Address.
#define PGADR_ 0xFE                     // 7-bit Flash page address, auto-clears.

sfr ERASE = 0x94;                       // Flash Erase.
#define PAGE_ERASE_ 0x55                // Initiate Flash Page Erase cycle..
                                        // ..must be proceeded by a write to PGADR.
#define MASS_ERASE_ 0xAA                // Initiate Flash Mass Erase cycle..
                                        // ..must be proceeded by a write to MEEN of FCTRL and..
                                        // ..the debug (CC) port must be enabled. 

#define FPAGE_SIZE 0x0200               // Size of Flash page in bytes.
#define FPAGE_MASK (FPAGE_SIZE-1)

// IFLAGS = 0xE8;                       // Enable of multiplexed interrupts.
sbit IE_PLLFALL = IFLAGS^7;             // Entering BROWNOUT mode   (use to read only, do not use to clear bit).
sbit IE_PLLRISE = IFLAGS^6;             // Leaving BROWNOUT mode    (use to read only, do not use to clear bit).
sbit IE_WAKE    = IFLAGS^5;             // Autotimer WAKEUP         (use to read only, do not use to clear bit).
sbit IE_PB      = IFLAGS^4;             // Push-Button WAKEUP       (use to read only, do not use to clear bit).
sbit IE_FWCOL1  = IFLAGS^3;             // Firmware collision w/ CE (use to read only, do not use to clear bit). 
sbit IE_FWCOL0  = IFLAGS^2;             // Firmware collision w/ CE (use to read only, do not use to clear bit). 
sbit IE_RTC     = IFLAGS^1;             // RTC ticked 				(use to read only, do not use to clear bit).
sbit IE_XFER    = IFLAGS^0;             // XFER data available 		(use to read only, do not use to clear bit).

#define IE_PLLFALL_     BIT7            // Entering BROWNOUT mode 	(use complement to clear).
#define IE_PLLRISE_     BIT6            // Leaving BROWNOUT mode  	(use complement to clear).
#define IE_WAKE_        BIT5            // Autotimer WAKEUP       	(use complement to clear).
#define IE_PB_          BIT4            // Push-Button WAKEUP     	(use complement to clear).
#define IE_FWCOL1_      BIT3            // Firmware collision w/ CE (use complement to clear).
#define IE_FWCOL0_      BIT2            // Firmware collision w/ CE (use complement to clear).
#define IE_RTC_         BIT1            // RTC ticked               (use complement to clear).
#define IE_XFER_        BIT0            // XFER data available	    (use complement to clear).

#define CLR_IE_PLLFALL()	IFLAGS = 0x7F & ~IE_PLLFALL_;
#define CLR_IE_PLLRISE()	IFLAGS = 0x7F & ~IE_PLLRISE_;
#define CLR_IE_WAKE()   	IFLAGS = 0x7F & ~IE_WAKE_;   
#define CLR_IE_PB()     	IFLAGS = 0x7F & ~IE_PB_;     
#define CLR_IE_FWCOL1() 	IFLAGS = 0x7F & ~IE_FWCOL1_; 
#define CLR_IE_FWCOL0() 	IFLAGS = 0x7F & ~IE_FWCOL0_; 
#define CLR_IE_XFER() 		IFLAGS = 0x7F & ~IE_XFER_;
#define CLR_IE_RTC() 		IFLAGS = 0x7F & ~IE_RTC_
#define WD_RST_         0xFF            // WatchDog bit.
#define RESET_WD() 		IFLAGS = WD_RST_;

// INTBIT = 0xF8;                       // Interrupt bits. Allows polling of external INT bits.
sbit INT_XFER_RTC = INTBIT^6;           // XFER    not busy and/or RTC on falling edge.
sbit INT_EEPROM   = INTBIT^5;           // EEPROM  not busy on edge low.
sbit INT_PLL      = INTBIT^4;           // PLL OK  on edge high, not OK on edge low.
sbit INT_CE_BUSY  = INTBIT^3;           // CE_BUSY on edge high, not BUSY on edge low.
sbit INT_FWCOL    = INTBIT^2;           // FWCOL   MPU/CE collison on edge high. 
sbit INT_IO_INT1  = INTBIT^1;           // IO_INT1 value of resource tied to INT1.
sbit INT_IO_INT0  = INTBIT^0;           // IO_INT0 value of resource tied to INT0.

#define INT_XFER_RTC_   BIT6            // XFER    not busy and/or RTC on falling edge.
#define INT_EEPROM_     BIT5            // EEPROM  not busy on edge low.
#define INT_PLL_        BIT4            // PLL OK  on edge high, not OK on edge low.
#define INT_CE_BUSY_    BIT3            // CE_BUSY on edge high, not BUSY on edge low.
#define INT_FWCOL_      BIT2            // FWCOL   MPU/CE collison on edge high. 
#define INT_IO_INT1_    BIT1            // IO_INT1 value of resource tied to INT1.
#define INT_IO_INT0_    BIT0            // IO_INT0 value of resource tied to INT0.


// Accumulator bits.
sbit   ACC_7 = ACC^7;
sbit   ACC_6 = ACC^6;
sbit   ACC_5 = ACC^5;
sbit   ACC_4 = ACC^4;
sbit   ACC_3 = ACC^3;
sbit   ACC_2 = ACC^2;
sbit   ACC_1 = ACC^1;
sbit   ACC_0 = ACC^0;

#define A   ACC
#define A_0 ACC_0
#define A_1 ACC_1
#define A_2 ACC_2
#define A_3 ACC_3
#define A_4 ACC_4
#define A_5 ACC_5
#define A_6 ACC_6
#define A_7 ACC_7

//===========================================================================//
#define CLK_STRETCH CKCON = STRETCH_6_
#define CLK_RELAX   CKCON = ck

// save interrupt and clock control state
#define CE_XFER_DEFINES \
    IRQ_DEFINES; \
    uint8_t ck = CKCON

// save interrupt and clock control state
#define CE_XFER_SAVE 

// manage both interrupts that read CE data
// should disable higher priorities first on entering
#define BEGIN_CE_CRITICAL_SECTION IRQ_DISABLE()

// should disable lower priorities first on exiting
#define END_CE_CRITICAL_SECTION IRQ_ENABLE()

/***************************************************************************
 * History:
 * $Log: reg652x.h,v $
 * Revision 1.33  2006/09/27 01:36:51  tvander
 * Added macro to test BATTERY_MODE_ENABLE (via DIO-8)
 *
 * Revision 1.32  2006/09/09 01:15:45  gmikef
 * *** empty log message ***
 *
 * Revision 1.31  2006/08/17 22:19:41  tvander
 * Reassigned PULSE3 and PULSE4 to DIO1 and DIO2.
 * Reassigned NEUTRAL_DETECTED to DIO16, which is at least free
 * on the demo PCB schematic.
 *
 * Revision 1.30  2006/06/14 02:48:09  tvander
 * Added comment
 *
 * Revision 1.29  2006/05/18 23:18:57  tvander
 * 16K and 32K
 * First cut at new requirements.
 * 32K 6521 is grossly tested.
 * All others have a clean compile with C51 8.02
 *
 * Revision 1.28  2006/04/27 00:06:58  tvander
 * Added tamper resistance, mostly to wh.c; Added a calibration signal to rtc.c
 *
 * Revision 1.27  2006/03/17 00:44:05  tvander
 * Clears of interrupt bits no longer reset watchdog interrupt.
 *
 * Revision 1.26  2006/02/08 22:54:47  gmikef
 * *** empty log message ***
 *
 * Revision 1.25  2006/01/25 01:28:00  tvander
 * WD_RESET() is correct; see I-20, 6520A02 team room.
 *
 * Revision 1.24  2006/01/17 03:26:03  gmikef
 * RESET_WD macro fixed. WD_RST_ now written to correct SFR INTBIT.
 *
 * Revision 1.23  2006/01/17 01:00:36  tvander
 * Added valid state of DIO_CAL, the input that triggers calibration.
 *
 * Revision 1.22  2006/01/10 04:13:18  gmikef
 * Added PDATA support for CE Outputs.
 *
 * Revision 1.21  2006/01/04 04:47:57  gmikef
 * Switched RMS and VA calculations to use floating point. (and Calibration).
 *
 * Revision 1.19  2005/12/10 04:07:45  tvander
 * Fixed 300 BAUD register constants for 4.2 mHz brownout mode.
 *
 * Revision 1.18  2005/12/07 01:47:58  tvander
 * RESET_WD() changed to match the change in spec.
 *
 * Revision 1.17  2005/10/08 04:41:32  tvander
 * Fixed priority inversion.
 * Rewrote watchdog to work in brownout, but of course it doesn't work.
 * Watchdog can now be defeated by clearing watchdog option to 0.
 * Reorganized watt hour modules (at last!).
 * Disabled reading of STATUS in 6521_cli because the CE's status is always SAG.
 * Tested with 6521_CLI; measurements seem to work.
 * Fixed other builds.
 *
 * Revision 1.16  2005/10/06 20:51:10  tvander
 * Added the brownout mode
 *
 * Revision 1.15  2005/09/28 00:55:01  tvander
 * Made the CE access macros smart about reading status in the CE busy interrupt.
 *
 * Revision 1.14  2005/09/22 23:45:28  tvander
 * Clean build all models and unit tests, updated copyright to be fore Teridian
 *
 * Revision 1.13  2005/09/01 04:25:47  gmikef
 * *** empty log message ***
 *
 * Revision 1.12  2005/08/12 06:04:03  gmikef
 * Added MPU temperature compensation for GAIN_ADJ.
 * Added changes to support new CE 6521 code.
 *
 * Revision 1.11  2005/08/10 02:06:45  gmikef
 * *** empty log message ***
 *
 * Revision 1.10  2005/06/10 22:57:09  tvander
 * Uses macros to reset watchdog and clear IE and RTC interrupts
 * Includes 6515 improvements in register defs.
 *
 * Revision 1.9  2005/05/13 00:34:48  tvander
 * 6511/32k works
 * Integrated and debugged self-calibration.
 * The build has one unused segment, and no other errors or warnings.
 * default LCD and pulse displays appear OK.
 * EEPROM, software timers and hardware timers are all integrated.
 *
 * Revision 1.8  2005/05/03 00:39:48  tvander
 * Incorporated event reporting in tmr0,tmr1 and unit tests.
 * Retested stm, trm0, tmr1.
 * Incorporated untested changes in io651x.h
 *
 * Revision 1.7  2005/04/30 02:20:09  gmikef
 * *** empty log message ***
 *
 * Revision 1.6  2005/04/28 19:01:08  tvander
 * Removed redundant include of reg80515.h
 *
 * Revision 1.5  2005/04/27 23:48:33  gmikef
 * Some MATH rountines now use 'idata'.
 * Added MATH_FAST flag to 'options.h".
 * Changed "6521B.Uv2" to max optimization.
 *
 * Revision 1.4  2005/04/21 02:08:39  gmikef
 * *** empty log message ***
 *
 * Revision 1.3  2005/04/06 23:34:38  tvander
 * Removed reg80515; it's a duplicate of the load in options.h
 *
 * Revision 1.2  2005/04/06 18:09:56  gmikef
 * *** empty log message ***
 *
 * Revision 1.1  2005/03/24 21:45:22  gmikef
 * *** empty log message ***
 *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 * this program is fully protected by the United States copyright          *
 * laws and is the property of Teridian Semiconductor Corporation.         *
 ***************************************************************************/
#endif /* reg652x.h */