?? tk_c64.asm
字號:
;*************************************************************************
; Copyright (c) 2004 TDK Semiconductor Corporation
; All Rights Reserved
; CONFIDENTIAL
;*************************************************************************
; Module Name : onek_c64.asm
; Description : For 64-pin package. Concatenate onek and onek_p2
; - CKOUT_E=3
; - flash size of 32K/16K/8K
;
; $Date: 2006/05/18 23:18:57 $
; $Revision: 1.2 $
; $Author: tvander $
;*************************************************************************
;***************************************************************************
; Registers and data definitions - This section will be in an include file
;***************************************************************************
;SFRs definition
USER1 DATA 090H ;user port 1
DIR1 DATA 091H ;user port 1 direction setting
IEN0 DATA 0A8H ;interrupt 0 enable reg.
IP0 DATA 0A9H ;interrupt priority 0 reg.
IEN1 DATA 0B8H ;interrupt 1 enable reg.
IP1 DATA 0B9H ;interrupt priority 1 reg.
T2CON DATA 0C8H ;bit6 controls polarity of int3, bit 5 controls int2
CKCON DATA 08EH
EA BIT IEN0.7 ;0=disable all interrupts
;*************************************************************************
; CSEG AT 00H
; ORG 00H
;POWERON: ;Power ON, hardware reset.
; SJMP POWERON
;*************************************************************************
; START - Start of main program
;*************************************************************************
CSEG AT 500H
ORG 500H
START:
CLR EA ;Disable interrupts.
;*************************************************************************
; DIO Tests begins
;*************************************************************************
; configure OPT_TX and OPT_RX as DIO[2:1]
MOV DPTR, #2008h
MOV A,#20h
MOVX @DPTR,A
MOV DPTR, #2007h
MOV A,#40h
MOVX @DPTR,A
; all DIO pins default to inputs
; configured as inputs first then changed to outputs
MOV A, 080h
MOV 0a2H, #0ffh ; change dio[7:1] to output
wait_dio_5a:
MOV 080h, A ; write back to dio[7:0]
ANL A, #0f7h
CJNE A, #052h, wait_dio_5a ;
MOV A, 090h
MOV 091h, #0ffh
MOV 090h, A
ANL A, #0cfh ; masking off dio[13:12]
CJNE A, #0c3h, err_dio ; c3 -> c3 after masking
MOV A, 0a0h
MOV 0a1h, #0ffh
MOV 0a0h, A
ANL A, #03 ; masking off dio[21:18]
CJNE A, #01h, err_dio ; 29h -> 01h after masking
; configured as inputs first then changed to outputs
MOV 0a2h, #0
MOV 091h, #0
MOV 0a1h, #0
MOV A, 080h
MOV 0a2H, #0ffh ; change dio[7:0] to output
wait_dio_a5:
MOV 080h, A ; write back to dio[7:0]
ANL A, #0f0h ; masking off dio[3:0]
CJNE A, #0a0h, wait_dio_5a ; a5 -> a0 after masking
MOV A, 090h
MOV 091h, #0ffh
MOV 090h, A
ANL A, #0cfh ; masking off dio[13:12]
CJNE A, #0ch, err_dio ; 3c -> 0c after masking
MOV A, 0a0h
MOV 0a1h, #0ffh
MOV 0a0h, A
ANL A, #03 ; masking off dio[21:18]
CJNE A, #02h, err_dio ; 16 -> 00 after masking
SJMP DIO_PASS
err_dio:
SJMP err_dio
; pulse DIO[16] if dio inputs check successfully
DIO_PASS:
MOV 0a0h, #01h
MOV 0a0h, #00h
;*************************************************************************
; check ROM/flash
; - output 8 parity bits thru {dio[7:4], dio[14],dio[10:8]} every 8 bytes
; - 41.2us per 8 bytes, if running clk_cpu @2.5MHz;
; total 336.192ms thru 32K memory, if flash_size=00;
; 16K, if flash_size=10; 8K, if flash_size=01
CHK_ROM:
MOV DPTR,#20fdh
MOV A,#04h
MOVX @DPTR,A
MOV DPTR,#20ffh
MOVX A,@DPTR
MOV DPTR,#0ffffh
MOV R1,#0 ; R1: parity byte
ANL A,#030h
JNZ chk_16K
MOV R2,#32
SJMP ROM_PAR
chk_16K:
CJNE A,#020h,size_8k
MOV R2,#16
SJMP ROM_PAR
size_8k:
MOV R2,#8
ROM_PAR:
MOV R3,#128 ; 1K bytes
total_1k:
MOV R0,#8
blk_parity:
CLR A
INC DPTR
MOVC A,@A+DPTR
XRL A,R1
MOV R1,A
DJNZ R0,blk_parity
MOV 80h, A ; dio[7:4]=parity[7:4],
; dio[3:0]=parity[3:0], if applicable
ANL A, #0fh
MOV R4, A
ANL A, #08h
RL A
RL A
RL A
ORL A, R4
MOV 90h, A ; dio[15]=1'b0, if applicable
; dio[14]=parity[3],
; dio[13:12]=2'b00, if applicable
; dio[11]=parity[3], if applicable
; dio[10:8]=parity[2:0]
MOV R1,#0
DJNZ R3,total_1k
DJNZ R2,ROM_PAR
; pulse DIO[16] to mark the end of ROM check
MOV 0a0h, #01h
MOV 0a0h, #00h
;*************************************************************************
; uP rams tests
;*************************************************************************
;/////////////////////////////////////////////
; internal data RAM
; - addressable space from 48 to 127
; initial addr
MOV R0,#30H
; initial dat
MOV R2,#00
wr_iram_inc:
; write addr 48 to 127 with incrementing pattern from 0 to 79
MOV A, R2
MOV @R0, A
INC R0
INC R2
CJNE R0, #80H, wr_iram_inc
; read and verify
MOV R0,#30H
MOV R2,#00
rd_iram_inc:
MOV A, @R0
MOV 80H, A
XRL A, R2
JNZ PULSE_ERR
INC R0
INC R2
CJNE R0, #80H, rd_iram_inc
; pulse DIO[16]
MOV 0a0h, #01h
MOV 0a0h, #00h
MOV R0, #30H
MOV R2, #79
wr_iram_dec:
; write addr 48 to 127 with decrementing pattern from 79 to 0
MOV A, R2
MOV @R0, A
INC R0
DEC R2
CJNE R0, #80H, wr_iram_dec
; read and verify
MOV R0,#30H
MOV R2,#79
rd_iram_dec:
CLR C
MOV A, @R0
MOV 80H, A
XRL A, R2
JNZ PULSE_ERR
INC R0
DEC R2
CJNE R0, #80H, rd_iram_dec
; pulse DIO[16]
MOV 0a0h, #01h
SJMP XRAM_TST
PULSE_ERR:
MOV 090H, #080H ; pulse DIO[15], otherwise
;/////////////////////////////////////////////
; XRAM
; - verify 255 pram locations per loop
XRAM_TST:
MOV 0A0H, #00H
MOV 090h, #00h
; looping idex (1 ~ 8)
MOV R2, #8
; initial DPH
MOV R3,#00H
; R4=0, incrementing patterns; R4=1, deccrementing patterns
xram_loop:
; write a block of 255 locations with incrementing pattern 2,...,255,0,1
LCALL wr_0t255_inc
; read and verify
MOV R4,#0
MOV R0,#0
MOV DPL, #00
LCALL rd_0t255
; write a block of 255 locations with decrementing pattern 1,0,255,...,2
LCALL wr_0t255_dec
; read and verify
MOV R4, #1
MOV R0,#255
MOV DPL, #00
LCALL rd_0t255
INC R3
DJNZ R2, xram_loop
;*********************************************************************
; CE rams test
;*********************************************************************
;/////////////////////////////////////////////
; CE data ram
; - ce ram addr 00 ~ 7f
; - verify 64 ram locations or 255 bytes per loop
; - ceram address 8'h0 to 8'h5 are not testable dur to fir control
; insert wait state
MOV CKCON, #06H
; looping idex (1 ~ 2)
MOV R2, #2
; initial DPH
MOV R3,#10H
; R4=0, incrementing patterns; R4=1, deccrementing patterns
cedram_loop:
; write a block of 64 locations with incrementing pattern 0 to 255
LCALL wr_0t255_inc
; read and verify
MOV R4,#0
LCALL rd_cdram_0t5
MOV R0,#24
MOV DPL, #24
LCALL rd_0t255
; write a block of 64 locations with decrementing pattern 255 to 0
LCALL wr_0t255_dec
; read and verify
MOV R4, #1
LCALL rd_cdram_0t5
MOV R0,#231
MOV DPL, #24
LCALL rd_0t255
; incrementing DPH
INC R3
DJNZ R2, cedram_loop
;/////////////////////////////////////////////
; for 6520, CE code ram merged into flash
; CE program ram
; - ce program ram addr 00(i.e.3000h) ~ 7ff(i.e. 3fff)
; - verify 128 pram locations or 255 bytes per loop
; clear wait state
;; MOV CKCON, #01H
; looping idex (1 ~ 16)
;; MOV R2, #16
; initial DPH
;; MOV R3,#30H
; R4=0, incrementing patterns; R4=1, deccrementing patterns
cepram_loop:
; write a block of 128 locations with incrementing pattern 0 to 255
;; LCALL wr_0t255_inc
; read and verify
;; MOV R4,#0
;; MOV R0,#0
;; MOV DPL, #00
;; LCALL rd_0t255
; write a block of 128 locations with decrementing pattern 255 to 0
;; LCALL wr_0t255_dec
; read and verify
;; MOV R4, #1
;; MOV R0,#255
;; MOV DPL, #00
;; LCALL rd_0t255
;; INC R3
;; DJNZ R2, cepram_loop
;FOREVERa:
; SJMP FOREVERa
LJMP FOREVER
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; functions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;//////////////////////////////////
; rams test functions
wr_0t255_inc:
; load incrementing 0,...,255
MOV A, R3
MOV DPH, A
MOV DPL, #00
MOV R0,#0
wr_0t255_inc_loop:
MOV A,R0
MOVX @DPTR,A
INC DPTR
INC R0
CJNE R0,#0,wr_0t255_inc_loop
RET
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
wr_0t255_dec:
; load incrementing 255,...,0
MOV A, R3
MOV DPH, A
MOV DPL, #00
MOV R0,#255
wr_0t255_dec_loop:
MOV A,R0
MOVX @DPTR,A
INC DPTR
DEC R0
CJNE R0,#255,wr_0t255_dec_loop
RET
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
rd_0t255:
MOV A, R3
MOV DPH, A
rd_0t255_loop:
MOVX A,@DPTR
MOV 80H, A
XRL A, R0
JNZ PULSE_ERRa
INC DPTR
CJNE R4, #0, dec_pattern
INC R0
CJNE R0,#0,rd_0t255_loop
SJMP pulse_dio16
dec_pattern:
DEC R0
CJNE R0,#255,rd_0t255_loop
pulse_dio16:
MOV 0a0h, #01h
SJMP rd_0t255_inc_done
PULSE_ERRa:
MOV 090H, #080H
rd_0t255_inc_done:
MOV 0A0H, #0
MOV 090h, #0
RET
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
rd_cdram_0t5:
MOV A, R3
MOV DPH, A
MOV DPL, #00
MOV R0, #24
dummy_rd_of_6:
MOVX A,@DPTR ; rd ce ram addr 0 to addr 5
;MOV 80H, A
INC DPTR
DJNZ R0, dummy_rd_of_6
RET
;*************************************************************************
; START - Start of part 2 main program
;*************************************************************************
ORG 698H
CLR EA ;Disable interrupts.
;*************************************************************************
; Tests begins
;*************************************************************************
; set CK_EN and CKOUT_DIS in test mode first, then exiting test mode
MOV DPTR,#2004H
MOV A,#30h
MOVX @DPTR,A
; LCD Control Reg
MOV DPTR,#2020H ;I/O RAM LCDX
MOV A,#012H ;LCD_NUM[4:0]=18d
MOVX @DPTR,A ;
MOV DPTR,#2022H ;LCDZ
MOV A,#1FH ;LCD_FS[4:0]=1Fh
MOVX @DPTR,A ;
; exercising lcd pins
MOV DPTR,#2030h
MOV R0,#42
MOV A,#05h
; writing 05H to all lcd pins for parameteric test
wr_seg_05:
MOVX @DPTR,A
INC DPTR
DJNZ R0,wr_seg_05
; enable lcd
MOV DPTR,#2021H ;I/O RAM LCDY
MOV A,#00100011B ;LCD_EN=1,LCD_MODE[2:0]=000b,LCD_CLK[1:0]=3h
MOVX @DPTR,A ;
MOV R4,#20
wait_8ms:
MOV R3,#255
wait_408us:
MUL AB
DJNZ R3,wait_408us
DJNZ R4,wait_8ms
; writing 0aH to all lcd pins for parameteric test
MOV DPTR,#2030h
MOV R0,#42
MOV A,#0ah
wr_seg_0a:
MOVX @DPTR,A
INC DPTR
DJNZ R0,wr_seg_0a
; 01-05-2005
; test lcd_fs=0
; first wait 8 ms
MOV R4,#20
wait_8ms_a:
MOV R3,#255
wait_408us_a:
MUL AB
DJNZ R3,wait_408us_a
DJNZ R4,wait_8ms_a
; then clr lcd_fs
MOV DPTR,#2022H ;LCDZ
MOV A,#00H ;LCD_FS[4:0]=00h
MOVX @DPTR,A
FOREVER:
SJMP FOREVER
END
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