/***************************************************************************
 * This code and information is provided "as is" without warranty of any   *
 * kind, either expressed or implied, including but not limited to the     *
 * implied warranties of merchantability and/or fitness for a particular   *
 * purpose.                                                                *
 *                                                                         *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 ***************************************************************************/
//**************************************************************************
//  DESCRIPTION: 71M652x POWER METER - I/O memory mapped SFR definitions.
// 
//  AUTHOR:  MTF
//
//  HISTORY: See end of file
//**************************************************************************
// File: IO652x.H
//
/* io652x special functions registers. */

#ifndef IO652X_H
#define IO652X_H 1

//  CKTEST is any test input frequency.
//  CK32  is 32768 Hz from XTAL.
//  RTCLK is 32768 Hz from XTAL.
//  CKADC is CK32 x 150 or CKTEST when CK_EN.
//  CKFIR is CKADC delayed.
//  CKCE  is CKADC.
//  CKMPU is derived from CKCE and MPU_DIV.
//  CKEM  is CKMPU x 2.
//  CKLCD is derived from CKADC and LCD_CLK.
//  CK32 drives MUX.

#define IO_BASE 0x2000        // Base of IO SFR RAM.

//==========================00=CE0 bit definitions===========================//
#define EQU              0xE0   // Specifies power equation.  See options.h
enum eEQU { 
// Meter characteristics           // Phase A         | Phase B | Phase C
    _1element_2wire = 0x00,        // VA IA           | VA IB   | N/A
    _1element_3wire = 0x20,        // VA (IA - IB)/ 2 | N/A     | N/A
    _2element_3wire = 0x40,        // VA IA           | VB IB   | N/A
};  

#define  CE_EN           BIT4   // Compute Engine Enable.
#define CE_ENABLE()      CE0 |= CE_EN; \
    IFLAGS = ~(IE_XFER_ | IE_RTC_)
#define CE_DISABLE()     CE0 &= ~CE_EN
#define CE_BUSY          INT_CE_BUSY
#define CE_ACTIVE        (CE0 & CE_EN)

enum eTMUX 						// Selects one of 32 inputs for TMUXOUT.
{
    _DGND,      // 0x00     // (analog)
    _IBIAS,     // 0x01     // (analog)
    _DGND2,     // 0x02     // (analog, from ATMUX)
    _VTHPN,     // 0x03     // (analog, from ATMUX)
    _PLL_2P5V,  // 0x04     // (analog, from ATMUX)
    _LPSTOUT,   // 0x05     // (analog, from ATMUX)	
    _VBIAS,     // 0x06     // (analog)
                // 0x07     // (unused)
    _REG_OK = 8,// 0x08
    _FUSE_OK,   // 0x09
    _COLDSTART, // 0x0A
    _ATEST0,    // 0x0B
    _ATEST1,    // 0x0C
    _ATEST2,    // 0x0D
    _ATEST3,    // 0x0E
    _ATEST4,    // 0x0F
                // 0x10..0x13 unused
    _RTM = 0x14,// 0x14     // (real time output from CE)
    _WDTR_E,    // 0x15     // (Comparator 1 output and V1LT3)
    _ALL_FETCH, // 0x16     // even parity of MPU and CE flash fetches
    _CE_FETCH,  // 0x17     // even parity of CE flash fetches
    _RXD = 0x18,// 0x18     // (from Optical interface, after optional inversion)
    _MUX_SYNC,  // 0x19     // (from MUX_CTRL)
    _CK_10M,    // 0x1A     //
    _CK_MPU,    // 0x1B     //
    _PULSE_OUT, // 0x1C     //
    _RTCLK_2_5, // 0x1D     //
    _CE_BUSY,   // 0x1E     //
    _XFER_BUSY  // 0x1F     //
};

//==========================01=CE1 bit definitions===========================//
#define  PRE_SAMPS       0xC0  // Duration of the pre-summer, in samples.
enum ePRE_SAMPS { _42 = 0x00, _50 = 0x40, _84 = 0x80, _100 = 0xC0 };  

#define  SUM_CYCLES      0x3F  // # of pre-summer outputs in the final summer.  

//==========================02=CE2 bit definitions===========================//
#define  MUX_DIV         0xC0  // States per MUX cycle.
enum eMUX_DIV { _6 = 0x00, _4 = 0x40, _3 = 0x80, _2 = 0xC0 };  

#define  CHOP_EN         0x30  // Chop enable.
enum eCHOP_EN { _POSITIVE = 0x10, _REVERSED = 0x20,  _ENABLED = 0x30};

#define  RTM_EN          BIT3  // Real Time Monitor enable (When '0', the RTM output is low).
#define  WD_OVF          BIT2  // WatchDog overflow indicator.    
#define  EX_RTC          BIT1  // Enable RTC interrupt.
#define  EX_XFER         BIT0  // Enable XFER interrupt.

//==========================03=COMP0 bit definitions=========================//
#define  PLL_OK          BIT6  // System is powered up, PLL is settled.
#define  COMP_STAT       BIT0  // V1_OK.

//==========================04=CONFIG0 bit definitions=======================//
#define  VREF_CAL        BIT7  // Brings VREF to VREF pad, VREF_DIS disables.
#define  PLS_INV         BIT6  // Inverts Pulse (Make active high).
#define  CKOUT_EN        0x30  // CKOUT Enable.
enum eCKOUT { SEG19 = 0x00, MHZ_5 = 0x10,  CKOUT = 0x20 };

#define  VREF_DIS        BIT3  // Disables the internal voltage reference.
#define  MPU_DIV         0x07  // MPU clock divider (from CKCE).
enum eMPU_DIV { _4915200Hz, _2457600Hz, _1228800Hz, _614400Hz,
                _307200Hz,  _153600Hz,  _76800Hz,   _38400Hz };

//==========================05=CONFIG1 bit definitions=======================//
#define  VDDREFZ        BIT7  // When zero, changes input reference of ADC to V3P3A, else its VBIAS.
#define  VB_REF         BIT6  // ADC used VB as zero reference.
#define  ECK_DIS        BIT5  // Emulator clock disable. When one, emulator clock is disabled.
#define  FIR_LEN        BIT4  // ADC decimation FIR filter length; 1-384 cycles, 0-288 cycles.
enum eADC_SIZE { _21_BIT = 0x00, _22_BIT = 0x10 };  // ADC size is set by FIR length. 

#define  ADC_EN         BIT3  // Enable ADC and adds bias current.
#define  MUX_ALT        BIT2  // 1 => MUX needs to perform TEMPERATURE sample.
#define  FLSH66ZT       BIT1  // 1 => 33ns flash read pulse; 0 => 66ns.   
//                      BIT0  // Reserved.

//==========================06=Chip Version==================================//
// 0x10 = 6520A01

//==========================07=CONFIG2 bit definitions=======================//
#define OPT_TXE          0xC0  // Configure OPT_TX as output pin.
enum eOPT_TXE { _OPT_TX = 0x00, _DIO2 = 0x40, _WPULSE = 0x80, _VARPULSE = 0xC0 };

#define  EX_PLL          BIT5  // Enable PLL (Brownout) interrupts. 
#define  EX_FWCOL        BIT4  // Enable Firmware collision interrupts.
#define  TMUXA           0x0C
enum eTMUXA { _GND = 0x00, _RTCLK = 0x04, _PLL_2_5 = 0x08, _LPTSTOUT = 0x0C };

#define  OPT_FDC         0x03  // OPT_TX modulation duty cycle low.
enum eOPT_FDC { _50percent, _25percent, _12_5percent, _6_25percent };

//==========================08=DIO0 bit definitions==========================//
#define DIO_EEX          0xC0  // Configure EEPROM interface.
//           DIO 4 & 5;         2-wire EEPROM;     3-wire EEPROM.
enum eDIO { DIO_EEX_DSB = 0x00, DIO_EEX_2W = 0x40, DIO_EEX_3W = 0x80 };

#define OPT_RXDIS        BIT5  // 0 => OPT_RX as analog input to optical UART.
#define OPT_RXINV        BIT4  // 1 => Invert input from OPT_RX.
#define DIO_PW           BIT3  // WPULSE   tied to DIO_6.
#define DIO_PV           BIT2  // VARPULSE tied to DIO_7.
#define OPT_TXMOD        BIT1  // 1 => Enable OPT_TX modulation.
#define OPT_TXINV        BIT0  // 1 => Invert output from OPT_TX.

//==========================09=DIO01 PB Resource Assignments=================//
//==========================0A=DIO-- 02 Resource Assignments=================//
//==========================0B=DIO05 04 Resource Assignments=================//
//==========================0C=DIO07 06 Resource Assignments=================//
//==========================0D=DIO09 08 Resource Assignments=================//
//==========================0E=DIO11 10 Resource Assignments=================//
#define DIO_R_EVEN       0x0F  // DIO pins PB, 1, 2 & 4 thru 11.
#define DIO_R_ODD        0xF0

enum eDIO_RESOURCE
{ 
    _NO_RESOURCE,              // I/O pin not tied to any internal resource.
    _Reserved,                 // Reserved.
    _T0,                       // Timer0 counter or gate.
    _T1,                       // Timer1 counter or gate.
    _IO_INT0_RISING,           // IO_INT0 interrupt rising.
    _IO_INT1_RISING,           // IO_INT1 interrupt rising.
    _IO_INT0_FALLING,          // IO_INT0 interrupt falling.
    _IO_INT1_FALLING           // IO_INT1 interrupt falling.
};

//==========================15=RTC_SEC ======================================//
//==========================16=RTC_MIN ======================================//
//==========================17=RTC_HR  ======================================//
//==========================18=RTC_DAY ======================================//
enum eDAY { SUN = 1, MON, TUE, WED, THU, FRI, SAT };

//==========================19=RTC_DATE======================================//
//==========================1A=RTC_MO  ======================================//
enum eMONTH { JAN = 1, FEB, MAR, APR, MAY, JUN, JUL, AUG, SEP, OCT, NOV, DEC };

//==========================1B=RTC_YEAR======================================//
//==========================1C=RTC_ADJUST====================================//
#define RTC_DEC_SEC      BIT1
#define RTC_INC_SEC      BIT0

//==========================1F=WE============================================//
// Reserved.

//==========================20=LCDX==========================================//
#define  BME			 BIT6  //
#define  FUSE_MISSION	 BIT5  //
#define  LCD_NUM         0x1F  // # of dual-purpose DIO pins configured as LCD.

//==========================21=LCDY==========================================//
#define  LCD_Y           BIT6  // Blink frequency 1 => 1.0 Hz; 0 => 0.5 Hz.
#define  LCD_EN          BIT5  // Enables the LCD display.

#define  LCD_MODE        0x1C  // The LCD bias mode.  
enum eLCD_MODE 
{ 
    BIAS_3rd_4_STATES  = 0x00, BIAS_3rd_3_STATES  = 0x04,
    BIAS_half_2_STATES = 0x08, BIAS_half_3_STATES = 0x0C, BIAS_STATIC = 0x10
};

#define  LCD_CLK         0x03  // Sets the LCD clock frequency.
enum eLCD_CLK { _75HZ, _150HZ, _300HZ, _600HZ };

//==========================22=LCDZ==========================================//
// Unused.

//==========================30=LCD0-38=======================================//
#define LCD_SEGS         0x0F  // Commons active for each segment.

//==========================5A=LCD_BLINK=====================================//
#define LCD_BLKMAP19     0xF0  // 1 => SEG19:common blinking; 0 => not blinking.
#define LCD_BLKMAP18     0x0F  // 1 => SEG18:common blinking; 0 => not blinking.

//==========================60=RTM===========================================//

//==========================80=PULSE_WIDTH===================================//
// (2 * PULSE_WIDTH + 1) * PULSE_INTERVAL * 812 nsec.     

//==========================81=PULSE_INTERVAL================================//
// PULSE_INTERVAL * 812 nsec.