module atd
(
 clk,
 reset,
 conv,
 data_in,
 converting,
 digit_out
);
 
 input clk;
 input reset;
 input conv;
 input [15:0]data_in;
 
 output converting;
 output [15:0]digit_out;
 
 parameter 
 minus_value_16 = 32768,
 minus_value_15 = 16384,
 minus_value_14 =  8192,
 minus_value_13 =  4096,
 minus_value_12 =  2048,
 minus_value_11 =  1024,
 minus_value_10 =   512,
 minus_value_9  =   256,
 minus_value_8  =   128,
 minus_value_7  =    64,
 minus_value_6  =    32,
 minus_value_5  =    16,
 minus_value_4  =     8,
 minus_value_3  =     4,
 minus_value_2  =     2,
 minus_value_1  =     1;
 
 reg
 num_of_digit16,
 num_of_digit15,
 num_of_digit14,
 num_of_digit13,
 num_of_digit12,
 num_of_digit11,
 num_of_digit10,
 num_of_digit9,
 num_of_digit8,
 num_of_digit7,
 num_of_digit6,
 num_of_digit5,
 num_of_digit4,
 num_of_digit3,
 num_of_digit2,
 num_of_digit1;
 reg [15:0]data_in_r;
 
 wire data_gteq_32768 = (data_in_r >= minus_value_16);
 wire data_gteq_16384 = (data_in_r >= minus_value_15);
 wire data_gteq_8192  = (data_in_r >= minus_value_14);
 wire data_gteq_4096  = (data_in_r >= minus_value_13);
 wire data_gteq_2048  = (data_in_r >= minus_value_12);
 wire data_gteq_1024  = (data_in_r >= minus_value_11);
 wire data_gteq_512   = (data_in_r >= minus_value_10);
 wire data_gteq_256   = (data_in_r >= minus_value_9);
 wire data_gteq_128   = (data_in_r >= minus_value_8);
 wire data_gteq_64    = (data_in_r >= minus_value_7);
 wire data_gteq_32    = (data_in_r >= minus_value_6);
 wire data_gteq_16    = (data_in_r >= minus_value_5);
 wire data_gteq_8     = (data_in_r >= minus_value_4);
 wire data_gteq_4     = (data_in_r >= minus_value_3);
 wire data_gteq_2     = (data_in_r >= minus_value_2);
 wire data_gteq_1     = (data_in_r >= minus_value_1);
 
 wire process_digit16 = data_gteq_32768;
 wire process_digit15 = ~data_gteq_32768 && data_gteq_16384;
 wire process_digit14 = ~data_gteq_16384 && data_gteq_8192;
 wire process_digit13 = ~data_gteq_8192 && data_gteq_4096;
 wire process_digit12 = ~data_gteq_4096 && data_gteq_2048;
 wire process_digit11 = ~data_gteq_2048 && data_gteq_1024;
 wire process_digit10 = ~data_gteq_1024 && data_gteq_512;
 wire process_digit9 = ~data_gteq_512 && data_gteq_256;
 wire process_digit8 = ~data_gteq_256 && data_gteq_128;
 wire process_digit7 = ~data_gteq_128 && data_gteq_64;
 wire process_digit6 = ~data_gteq_64 && data_gteq_32;
 wire process_digit5 = ~data_gteq_32 && data_gteq_16;
 wire process_digit4 = ~data_gteq_16 && data_gteq_8;
 wire process_digit3 = ~data_gteq_8 && data_gteq_4;
 wire process_digit2 = ~data_gteq_4 && data_gteq_2;
 wire process_digit1 = ~data_gteq_2 && data_gteq_1;
 
 always@(posedge clk)
 begin
 	if(reset ||  conv)
 		data_in_r <= reset ? 16'b0 : conv ? data_in : data_in_r;
 	else
 		case(1'b1)
 			process_digit16 : data_in_r <= data_in_r - minus_value_16;
 			process_digit15 : data_in_r <= data_in_r - minus_value_15;
 			process_digit14 : data_in_r <= data_in_r - minus_value_14;
 			process_digit13 : data_in_r <= data_in_r - minus_value_13;
 			process_digit12 : data_in_r <= data_in_r - minus_value_12;
 			process_digit11 : data_in_r <= data_in_r - minus_value_11;
 			process_digit10 : data_in_r <= data_in_r - minus_value_10;
 			process_digit9 : data_in_r <= data_in_r - minus_value_9;
 			process_digit8 : data_in_r <= data_in_r - minus_value_8;
 			process_digit7 : data_in_r <= data_in_r - minus_value_7;
 			process_digit6 : data_in_r <= data_in_r - minus_value_6;
 			process_digit5 : data_in_r <= data_in_r - minus_value_5;
 			process_digit4 : data_in_r <= data_in_r - minus_value_4;
 			process_digit3 : data_in_r <= data_in_r - minus_value_3;
 			process_digit2 : data_in_r <= data_in_r - minus_value_2;
 			process_digit1 : data_in_r <= data_in_r - minus_value_1;
 		endcase
 end
 
 always@(posedge clk)
 begin
 	if(reset || conv)
 		begin
 			num_of_digit16 <= 0;
 			num_of_digit15 <= 0;
 			num_of_digit14 <= 0;
 			num_of_digit13 <= 0;
 			num_of_digit12 <= 0;
 			num_of_digit11 <= 0;
 			num_of_digit10 <= 0;
 			num_of_digit9 <= 0;
 			num_of_digit8 <= 0;
 			num_of_digit7 <= 0;
 			num_of_digit6 <= 0;
 			num_of_digit5 <= 0;
 			num_of_digit4 <= 0;
 			num_of_digit3 <= 0;
 			num_of_digit2 <= 0;
 			num_of_digit1 <= 0;
 		end
 	else
 		case(1'b1)
 			process_digit16 : num_of_digit16 <= 1'b1;
 			process_digit15 : num_of_digit15 <= 1'b1;
 			process_digit14 : num_of_digit14 <= 1'b1;
 			process_digit13 : num_of_digit13 <= 1'b1;
 			process_digit12 : num_of_digit12 <= 1'b1;
 			process_digit11 : num_of_digit11 <= 1'b1;
 			process_digit10 : num_of_digit10 <= 1'b1;
 			process_digit9 : num_of_digit9 <= 1'b1;
 			process_digit8 : num_of_digit8 <= 1'b1;
 			process_digit7 : num_of_digit7 <= 1'b1;
 			process_digit6 : num_of_digit6 <= 1'b1;
 			process_digit5 : num_of_digit5 <= 1'b1;
 			process_digit4 : num_of_digit4 <= 1'b1;
 			process_digit3 : num_of_digit3 <= 1'b1;
 			process_digit2 : num_of_digit2 <= 1'b1;
 			process_digit1 : num_of_digit1 <= 1'b1;
 		endcase
 end
 
 assign digit_out = {   num_of_digit16,
			num_of_digit15,
 			num_of_digit14,
 			num_of_digit13,
 			num_of_digit12,
 			num_of_digit11,
 			num_of_digit10,
 			num_of_digit9,
 			num_of_digit8,
 			num_of_digit7,
 			num_of_digit6,
 			num_of_digit5,
 			num_of_digit4,
 			num_of_digit3,
 			num_of_digit2,
 			num_of_digit1  };
 assign converting = (~|data_in_r
 			/*process_digit16 |
 			process_digit15 |
 			process_digit14 |
 			process_digit13 |
 			process_digit12 |
 			process_digit11 |
 			process_digit10 |
 			process_digit9 |
 			process_digit8 |
 			process_digit7 |
 			process_digit6 |
 			process_digit5 |
 			process_digit4 |
 			process_digit3 |
 			process_digit2 |
 			process_digit1 */  );
 endmodule