L1_q[5]_lut_out = A1L69;
L1_q[5] = DFFEA(L1_q[5]_lut_out, inst22, VCC, , , , );


--F1L78 is control1:inst3|regSel[2]~1189
--operation mode is normal

F1L78 = L1_q[12] & (L1_q[11] $ L1_q[13]) # !L1_q[12] & L1_q[11] & !L1_q[13];


--F1L77 is control1:inst3|regSel[0]~1190
--operation mode is normal

F1L77 = L1_q[12] & (L1_q[11] $ !L1_q[13]);


--F1L88 is control1:inst3|regSel[2]~1191
--operation mode is normal

F1L88 = L1_q[2] & (F1L77 # L1_q[5] & F1L78) # !L1_q[2] & L1_q[5] & F1L78;


--F1L98 is control1:inst3|regSel[2]~1192
--operation mode is normal

F1L98 = F1L86 & (F1L88 # L1_q[5] & !F1L27) # !F1L86 & L1_q[5] & !F1L27;


--K1_ramdata[2][13] is regarray:inst10|ramdata[2][13]
--operation mode is normal

K1_ramdata[2][13]_lut_out = A1L621;
K1_ramdata[2][13] = DFFEA(K1_ramdata[2][13]_lut_out, inst11, VCC, , K1L3, , );


--L1_q[4] is reg:inst12|q[4]
--operation mode is normal

L1_q[4]_lut_out = A1L39;
L1_q[4] = DFFEA(L1_q[4]_lut_out, inst22, VCC, , , , );


--F1L28 is control1:inst3|regSel[1]~1193
--operation mode is normal

F1L28 = L1_q[4] & (L1_q[11] & !L1_q[13] # !L1_q[11] & L1_q[12] & L1_q[13]);


--L1_q[1] is reg:inst12|q[1]
--operation mode is normal

L1_q[1]_lut_out = A1L48;
L1_q[1] = DFFEA(L1_q[1]_lut_out, inst22, VCC, , , , );


--F1L38 is control1:inst3|regSel[1]~1194
--operation mode is normal

F1L38 = F1L86 & (F1L28 # F1L77 & L1_q[1]);


--F1L17 is control1:inst3|reduce_or~23
--operation mode is normal

F1L17 = F1L81Q # F1L32Q # F1L55Q # !F1L37;


--F1L48 is control1:inst3|regSel[1]~1195
--operation mode is normal

F1L48 = F1L17 & (L1_q[1] # L1_q[4] & !F1L27) # !F1L17 & L1_q[4] & !F1L27;


--F1L58 is control1:inst3|regSel[1]~1196
--operation mode is normal

F1L58 = F1L38 # F1L48 # F1L25Q & L1_q[1];


--K1_ramdata[1][13] is regarray:inst10|ramdata[1][13]
--operation mode is normal

K1_ramdata[1][13]_lut_out = A1L621;
K1_ramdata[1][13] = DFFEA(K1_ramdata[1][13]_lut_out, inst11, VCC, , K1L2, , );


--L1_q[3] is reg:inst12|q[3]
--operation mode is normal

L1_q[3]_lut_out = A1L09;
L1_q[3] = DFFEA(L1_q[3]_lut_out, inst22, VCC, , , , );


--F1L87 is control1:inst3|regSel[0]~1197
--operation mode is normal

F1L87 = L1_q[3] & (L1_q[11] & !L1_q[13] # !L1_q[11] & L1_q[12] & L1_q[13]);


--L1_q[0] is reg:inst12|q[0]
--operation mode is normal

L1_q[0]_lut_out = A1L08;
L1_q[0] = DFFEA(L1_q[0]_lut_out, inst22, VCC, , , , );


--F1L97 is control1:inst3|regSel[0]~1198
--operation mode is normal

F1L97 = F1L86 & (F1L87 # F1L77 & L1_q[0]);


--F1L08 is control1:inst3|regSel[0]~1199
--operation mode is normal

F1L08 = F1L17 & (L1_q[0] # L1_q[3] & !F1L27) # !F1L17 & L1_q[3] & !F1L27;


--F1L18 is control1:inst3|regSel[0]~1200
--operation mode is normal

F1L18 = F1L97 # F1L08 # F1L25Q & L1_q[0];


--K1_ramdata[0][13] is regarray:inst10|ramdata[0][13]
--operation mode is normal

K1_ramdata[0][13]_lut_out = A1L621;
K1_ramdata[0][13] = DFFEA(K1_ramdata[0][13]_lut_out, inst11, VCC, , K1L1, , );


--K1L502 is regarray:inst10|temp_data[13]~88
--operation mode is normal

K1L502 = F1L18 & (F1L58 # K1_ramdata[1][13]) # !F1L18 & !F1L58 & K1_ramdata[0][13];


--K1_ramdata[3][13] is regarray:inst10|ramdata[3][13]
--operation mode is normal

K1_ramdata[3][13]_lut_out = A1L621;
K1_ramdata[3][13] = DFFEA(K1_ramdata[3][13]_lut_out, inst11, VCC, , K1L4, , );


--K1L602 is regarray:inst10|temp_data[13]~89
--operation mode is normal

K1L602 = K1L502 & (K1_ramdata[3][13] # !F1L58) # !K1L502 & K1_ramdata[2][13] & F1L58;


--K1_ramdata[5][13] is regarray:inst10|ramdata[5][13]
--operation mode is normal

K1_ramdata[5][13]_lut_out = A1L621;
K1_ramdata[5][13] = DFFEA(K1_ramdata[5][13]_lut_out, inst11, VCC, , K1L6, , );


--K1_ramdata[6][13] is regarray:inst10|ramdata[6][13]
--operation mode is normal

K1_ramdata[6][13]_lut_out = A1L621;
K1_ramdata[6][13] = DFFEA(K1_ramdata[6][13]_lut_out, inst11, VCC, , K1L7, , );


--K1_ramdata[4][13] is regarray:inst10|ramdata[4][13]
--operation mode is normal

K1_ramdata[4][13]_lut_out = A1L621;
K1_ramdata[4][13] = DFFEA(K1_ramdata[4][13]_lut_out, inst11, VCC, , K1L5, , );


--K1L702 is regarray:inst10|temp_data[13]~90
--operation mode is normal

K1L702 = F1L58 & (F1L18 # K1_ramdata[6][13]) # !F1L58 & !F1L18 & K1_ramdata[4][13];


--K1_ramdata[7][13] is regarray:inst10|ramdata[7][13]
--operation mode is normal

K1_ramdata[7][13]_lut_out = A1L621;
K1_ramdata[7][13] = DFFEA(K1_ramdata[7][13]_lut_out, inst11, VCC, , K1L8, , );


--K1L802 is regarray:inst10|temp_data[13]~91
--operation mode is normal

K1L802 = K1L702 & (K1_ramdata[7][13] # !F1L18) # !K1L702 & K1_ramdata[5][13] & F1L18;


--A1L521 is gdfx_temp0[13]~1344
--operation mode is normal

A1L521 = F1L68 & !K1L802 # !F1L68 & (F1L98 & !K1L802 # !F1L98 & !K1L602);


--A1L621 is gdfx_temp0[13]~1345
--operation mode is normal

A1L621 = A1L321 & A1L421 & (!A1L521 # !F1L67);


--M3_q[15] is reg_l:inst21|q[15]
--operation mode is normal

M3_q[15]_lut_out = A1L531;
M3_q[15] = DFFEA(M3_q[15]_lut_out, E1_inst11, !RST, , F1L43Q, , );


--K1_ramdata[2][15] is regarray:inst10|ramdata[2][15]
--operation mode is normal

K1_ramdata[2][15]_lut_out = A1L531;
K1_ramdata[2][15] = DFFEA(K1_ramdata[2][15]_lut_out, inst11, VCC, , K1L3, , );


--K1_ramdata[1][15] is regarray:inst10|ramdata[1][15]
--operation mode is normal

K1_ramdata[1][15]_lut_out = A1L531;
K1_ramdata[1][15] = DFFEA(K1_ramdata[1][15]_lut_out, inst11, VCC, , K1L2, , );


--K1_ramdata[0][15] is regarray:inst10|ramdata[0][15]
--operation mode is normal

K1_ramdata[0][15]_lut_out = A1L531;
K1_ramdata[0][15] = DFFEA(K1_ramdata[0][15]_lut_out, inst11, VCC, , K1L1, , );


--K1L312 is regarray:inst10|temp_data[15]~92
--operation mode is normal

K1L312 = F1L18 & (F1L58 # K1_ramdata[1][15]) # !F1L18 & !F1L58 & K1_ramdata[0][15];


--K1_ramdata[3][15] is regarray:inst10|ramdata[3][15]
--operation mode is normal

K1_ramdata[3][15]_lut_out = A1L531;
K1_ramdata[3][15] = DFFEA(K1_ramdata[3][15]_lut_out, inst11, VCC, , K1L4, , );


--K1L412 is regarray:inst10|temp_data[15]~93
--operation mode is normal

K1L412 = K1L312 & (K1_ramdata[3][15] # !F1L58) # !K1L312 & K1_ramdata[2][15] & F1L58;


--K1_ramdata[5][15] is regarray:inst10|ramdata[5][15]
--operation mode is normal

K1_ramdata[5][15]_lut_out = A1L531;
K1_ramdata[5][15] = DFFEA(K1_ramdata[5][15]_lut_out, inst11, VCC, , K1L6, , );


--K1_ramdata[6][15] is regarray:inst10|ramdata[6][15]
--operation mode is normal

K1_ramdata[6][15]_lut_out = A1L531;
K1_ramdata[6][15] = DFFEA(K1_ramdata[6][15]_lut_out, inst11, VCC, , K1L7, , );


--K1_ramdata[4][15] is regarray:inst10|ramdata[4][15]
--operation mode is normal

K1_ramdata[4][15]_lut_out = A1L531;
K1_ramdata[4][15] = DFFEA(K1_ramdata[4][15]_lut_out, inst11, VCC, , K1L5, , );


--K1L512 is regarray:inst10|temp_data[15]~94
--operation mode is normal

K1L512 = F1L58 & (F1L18 # K1_ramdata[6][15]) # !F1L58 & !F1L18 & K1_ramdata[4][15];


--K1_ramdata[7][15] is regarray:inst10|ramdata[7][15]
--operation mode is normal

K1_ramdata[7][15]_lut_out = A1L531;
K1_ramdata[7][15] = DFFEA(K1_ramdata[7][15]_lut_out, inst11, VCC, , K1L8, , );


--K1L612 is regarray:inst10|temp_data[15]~95
--operation mode is normal

K1L612 = K1L512 & (K1_ramdata[7][15] # !F1L18) # !K1L512 & K1_ramdata[5][15] & F1L18;


--A1L131 is gdfx_temp0[15]~1346
--operation mode is normal

A1L131 = F1L68 & !K1L612 # !F1L68 & (F1L98 & !K1L612 # !F1L98 & !K1L412);


--A1L231 is gdfx_temp0[15]~1347
--operation mode is normal

A1L231 = F1L37 & !F1L57 # !A1L131;


--YB1_q_a[15] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[15]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[15]_PORT_A_data_in = A1L531;
YB1_q_a[15]_PORT_A_data_in_reg = DFFE(YB1_q_a[15]_PORT_A_data_in, YB1_q_a[15]_clock_0, , , );
YB1_q_a[15]_PORT_B_data_in = ZB1_ram_rom_data_reg[15];
YB1_q_a[15]_PORT_B_data_in_reg = DFFE(YB1_q_a[15]_PORT_B_data_in, YB1_q_a[15]_clock_1, , , );
YB1_q_a[15]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[15]_PORT_A_address_reg = DFFE(YB1_q_a[15]_PORT_A_address, YB1_q_a[15]_clock_0, , , );
YB1_q_a[15]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[15]_PORT_B_address_reg = DFFE(YB1_q_a[15]_PORT_B_address, YB1_q_a[15]_clock_1, , , );
YB1_q_a[15]_PORT_A_write_enable = F1L02Q;
YB1_q_a[15]_PORT_A_write_enable_reg = DFFE(YB1_q_a[15]_PORT_A_write_enable, YB1_q_a[15]_clock_0, , , );
YB1_q_a[15]_PORT_B_write_enable = ZB1L83;
YB1_q_a[15]_PORT_B_write_enable_reg = DFFE(YB1_q_a[15]_PORT_B_write_enable, YB1_q_a[15]_clock_1, , , );
YB1_q_a[15]_clock_0 = E1_inst11;
YB1_q_a[15]_clock_1 = A1L51;
YB1_q_a[15]_PORT_A_data_out = MEMORY(YB1_q_a[15]_PORT_A_data_in_reg, YB1_q_a[15]_PORT_B_data_in_reg, YB1_q_a[15]_PORT_A_address_reg, YB1_q_a[15]_PORT_B_address_reg, YB1_q_a[15]_PORT_A_write_enable_reg, YB1_q_a[15]_PORT_B_write_enable_reg, , , YB1_q_a[15]_clock_0, YB1_q_a[15]_clock_1, , , , );
YB1_q_a[15] = YB1_q_a[15]_PORT_A_data_out[0];

--YB1_q_b[15] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[15]
YB1_q_b[15]_PORT_A_data_in = A1L531;
YB1_q_b[15]_PORT_A_data_in_reg = DFFE(YB1_q_b[15]_PORT_A_data_in, YB1_q_b[15]_clock_0, , , );
YB1_q_b[15]_PORT_B_data_in = ZB1_ram_rom_data_reg[15];
YB1_q_b[15]_PORT_B_data_in_reg = DFFE(YB1_q_b[15]_PORT_B_data_in, YB1_q_b[15]_clock_1, , , );
YB1_q_b[15]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[15]_PORT_A_address_reg = DFFE(YB1_q_b[15]_PORT_A_address, YB1_q_b[15]_clock_0, , , );
YB1_q_b[15]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[15]_PORT_B_address_reg = DFFE(YB1_q_b[15]_PORT_B_address, YB1_q_b[15]_clock_1, , , );
YB1_q_b[15]_PORT_A_write_enable = F1L02Q;
YB1_q_b[15]_PORT_A_write_enable_reg = DFFE(YB1_q_b[15]_PORT_A_write_enable, YB1_q_b[15]_clock_0, , , );
YB1_q_b[15]_PORT_B_write_enable = ZB1L83;
YB1_q_b[15]_PORT_B_write_enable_reg = DFFE(YB1_q_b[15]_PORT_B_write_enable, YB1_q_b[15]_clock_1, , , );
YB1_q_b[15]_clock_0 = E1_inst11;
YB1_q_b[15]_clock_1 = A1L51;
YB1_q_b[15]_PORT_B_data_out = MEMORY(YB1_q_b[15]_PORT_A_data_in_reg, YB1_q_b[15]_PORT_B_data_in_reg, YB1_q_b[15]_PORT_A_address_reg, YB1_q_b[15]_PORT_B_address_reg, YB1_q_b[15]_PORT_A_write_enable_reg, YB1_q_b[15]_PORT_B_write_enable_reg, , , YB1_q_b[15]_clock_0, YB1_q_b[15]_clock_1, , , , );
YB1_q_b[15] = YB1_q_b[15]_PORT_B_data_out[0];


--A1L331 is gdfx_temp0[15]~1348
--operation mode is normal

A1L331 = YB1_q_a[15] & (in[15] # !M1_q[15]) # !F1L59;


--M2_q[15] is reg_l:inst17|q[15]
--operation mode is normal

M2_q[15]_lut_out = A1L531;
M2_q[15] = DFFEA(M2_q[15]_lut_out, E1_inst8, !RST, , F1L07, , );


--H1_val[15] is trireg:inst7|val[15]
--operation mode is normal

H1_val[15]_lut_out = C1L33;
H1_val[15] = DFFEA(H1_val[15]_lut_out, inst20, VCC, , , , );


--A1L431 is gdfx_temp0[15]~1349
--operation mode is normal

A1L431 = M2_q[15] & (H1_val[15] # !F1_outRegRd) # !M2_q[15] & !F1L76 & (H1_val[15] # !F1_outRegRd);


--D1L34 is comp:inst1|nequal~15
--operation mode is normal

D1L34 = M3_q[15] $ (A1L231 & A1L331 & A1L431);


--D1L2 is comp:inst1|compout~263
--operation mode is normal

D1L2 = F1L8 & !D1L34 & (M3_q[13] $ !A1L621);


--M3_q[9] is reg_l:inst21|q[9]
--operation mode is normal

M3_q[9]_lut_out = A1L011;
M3_q[9] = DFFEA(M3_q[9]_lut_out, E1_inst11, !RST, , F1L43Q, , );


--YB1_q_a[9] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[9]_PORT_A_data_in = A1L011;
YB1_q_a[9]_PORT_A_data_in_reg = DFFE(YB1_q_a[9]_PORT_A_data_in, YB1_q_a[9]_clock_0, , , );
YB1_q_a[9]_PORT_B_data_in = ZB1_ram_rom_data_reg[9];
YB1_q_a[9]_PORT_B_data_in_reg = DFFE(YB1_q_a[9]_PORT_B_data_in, YB1_q_a[9]_clock_1, , , );
YB1_q_a[9]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);