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YB1_q_a[9]_PORT_A_address_reg = DFFE(YB1_q_a[9]_PORT_A_address, YB1_q_a[9]_clock_0, , , );
YB1_q_a[9]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[9]_PORT_B_address_reg = DFFE(YB1_q_a[9]_PORT_B_address, YB1_q_a[9]_clock_1, , , );
YB1_q_a[9]_PORT_A_write_enable = F1L02Q;
YB1_q_a[9]_PORT_A_write_enable_reg = DFFE(YB1_q_a[9]_PORT_A_write_enable, YB1_q_a[9]_clock_0, , , );
YB1_q_a[9]_PORT_B_write_enable = ZB1L83;
YB1_q_a[9]_PORT_B_write_enable_reg = DFFE(YB1_q_a[9]_PORT_B_write_enable, YB1_q_a[9]_clock_1, , , );
YB1_q_a[9]_clock_0 = E1_inst11;
YB1_q_a[9]_clock_1 = A1L51;
YB1_q_a[9]_PORT_A_data_out = MEMORY(YB1_q_a[9]_PORT_A_data_in_reg, YB1_q_a[9]_PORT_B_data_in_reg, YB1_q_a[9]_PORT_A_address_reg, YB1_q_a[9]_PORT_B_address_reg, YB1_q_a[9]_PORT_A_write_enable_reg, YB1_q_a[9]_PORT_B_write_enable_reg, , , YB1_q_a[9]_clock_0, YB1_q_a[9]_clock_1, , , , );
YB1_q_a[9] = YB1_q_a[9]_PORT_A_data_out[0];

--YB1_q_b[9] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[9]
YB1_q_b[9]_PORT_A_data_in = A1L011;
YB1_q_b[9]_PORT_A_data_in_reg = DFFE(YB1_q_b[9]_PORT_A_data_in, YB1_q_b[9]_clock_0, , , );
YB1_q_b[9]_PORT_B_data_in = ZB1_ram_rom_data_reg[9];
YB1_q_b[9]_PORT_B_data_in_reg = DFFE(YB1_q_b[9]_PORT_B_data_in, YB1_q_b[9]_clock_1, , , );
YB1_q_b[9]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[9]_PORT_A_address_reg = DFFE(YB1_q_b[9]_PORT_A_address, YB1_q_b[9]_clock_0, , , );
YB1_q_b[9]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[9]_PORT_B_address_reg = DFFE(YB1_q_b[9]_PORT_B_address, YB1_q_b[9]_clock_1, , , );
YB1_q_b[9]_PORT_A_write_enable = F1L02Q;
YB1_q_b[9]_PORT_A_write_enable_reg = DFFE(YB1_q_b[9]_PORT_A_write_enable, YB1_q_b[9]_clock_0, , , );
YB1_q_b[9]_PORT_B_write_enable = ZB1L83;
YB1_q_b[9]_PORT_B_write_enable_reg = DFFE(YB1_q_b[9]_PORT_B_write_enable, YB1_q_b[9]_clock_1, , , );
YB1_q_b[9]_clock_0 = E1_inst11;
YB1_q_b[9]_clock_1 = A1L51;
YB1_q_b[9]_PORT_B_data_out = MEMORY(YB1_q_b[9]_PORT_A_data_in_reg, YB1_q_b[9]_PORT_B_data_in_reg, YB1_q_b[9]_PORT_A_address_reg, YB1_q_b[9]_PORT_B_address_reg, YB1_q_b[9]_PORT_A_write_enable_reg, YB1_q_b[9]_PORT_B_write_enable_reg, , , YB1_q_b[9]_clock_0, YB1_q_b[9]_clock_1, , , , );
YB1_q_b[9] = YB1_q_b[9]_PORT_B_data_out[0];


--A1L701 is gdfx_temp0[9]~1350
--operation mode is normal

A1L701 = YB1_q_a[9] & (in[9] # !M1_q[15]) # !F1L59;


--M2_q[9] is reg_l:inst17|q[9]
--operation mode is normal

M2_q[9]_lut_out = A1L011;
M2_q[9] = DFFEA(M2_q[9]_lut_out, E1_inst8, !RST, , F1L07, , );


--H1_val[9] is trireg:inst7|val[9]
--operation mode is normal

H1_val[9]_lut_out = C1L74;
H1_val[9] = DFFEA(H1_val[9]_lut_out, inst20, VCC, , , , );


--A1L801 is gdfx_temp0[9]~1351
--operation mode is normal

A1L801 = M2_q[9] & (H1_val[9] # !F1_outRegRd) # !M2_q[9] & !F1L76 & (H1_val[9] # !F1_outRegRd);


--K1_ramdata[2][9] is regarray:inst10|ramdata[2][9]
--operation mode is normal

K1_ramdata[2][9]_lut_out = A1L011;
K1_ramdata[2][9] = DFFEA(K1_ramdata[2][9]_lut_out, inst11, VCC, , K1L3, , );


--K1_ramdata[1][9] is regarray:inst10|ramdata[1][9]
--operation mode is normal

K1_ramdata[1][9]_lut_out = A1L011;
K1_ramdata[1][9] = DFFEA(K1_ramdata[1][9]_lut_out, inst11, VCC, , K1L2, , );


--K1_ramdata[0][9] is regarray:inst10|ramdata[0][9]
--operation mode is normal

K1_ramdata[0][9]_lut_out = A1L011;
K1_ramdata[0][9] = DFFEA(K1_ramdata[0][9]_lut_out, inst11, VCC, , K1L1, , );


--K1L981 is regarray:inst10|temp_data[9]~80
--operation mode is normal

K1L981 = F1L18 & (F1L58 # K1_ramdata[1][9]) # !F1L18 & !F1L58 & K1_ramdata[0][9];


--K1_ramdata[3][9] is regarray:inst10|ramdata[3][9]
--operation mode is normal

K1_ramdata[3][9]_lut_out = A1L011;
K1_ramdata[3][9] = DFFEA(K1_ramdata[3][9]_lut_out, inst11, VCC, , K1L4, , );


--K1L091 is regarray:inst10|temp_data[9]~81
--operation mode is normal

K1L091 = K1L981 & (K1_ramdata[3][9] # !F1L58) # !K1L981 & K1_ramdata[2][9] & F1L58;


--K1_ramdata[5][9] is regarray:inst10|ramdata[5][9]
--operation mode is normal

K1_ramdata[5][9]_lut_out = A1L011;
K1_ramdata[5][9] = DFFEA(K1_ramdata[5][9]_lut_out, inst11, VCC, , K1L6, , );


--K1_ramdata[6][9] is regarray:inst10|ramdata[6][9]
--operation mode is normal

K1_ramdata[6][9]_lut_out = A1L011;
K1_ramdata[6][9] = DFFEA(K1_ramdata[6][9]_lut_out, inst11, VCC, , K1L7, , );


--K1_ramdata[4][9] is regarray:inst10|ramdata[4][9]
--operation mode is normal

K1_ramdata[4][9]_lut_out = A1L011;
K1_ramdata[4][9] = DFFEA(K1_ramdata[4][9]_lut_out, inst11, VCC, , K1L5, , );


--K1L191 is regarray:inst10|temp_data[9]~82
--operation mode is normal

K1L191 = F1L58 & (F1L18 # K1_ramdata[6][9]) # !F1L58 & !F1L18 & K1_ramdata[4][9];


--K1_ramdata[7][9] is regarray:inst10|ramdata[7][9]
--operation mode is normal

K1_ramdata[7][9]_lut_out = A1L011;
K1_ramdata[7][9] = DFFEA(K1_ramdata[7][9]_lut_out, inst11, VCC, , K1L8, , );


--K1L291 is regarray:inst10|temp_data[9]~83
--operation mode is normal

K1L291 = K1L191 & (K1_ramdata[7][9] # !F1L18) # !K1L191 & K1_ramdata[5][9] & F1L18;


--A1L901 is gdfx_temp0[9]~1352
--operation mode is normal

A1L901 = F1L68 & !K1L291 # !F1L68 & (F1L98 & !K1L291 # !F1L98 & !K1L091);


--A1L011 is gdfx_temp0[9]~1353
--operation mode is normal

A1L011 = A1L701 & A1L801 & (!A1L901 # !F1L67);


--YB1_q_a[3] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[3]_PORT_A_data_in = A1L09;
YB1_q_a[3]_PORT_A_data_in_reg = DFFE(YB1_q_a[3]_PORT_A_data_in, YB1_q_a[3]_clock_0, , , );
YB1_q_a[3]_PORT_B_data_in = ZB1_ram_rom_data_reg[3];
YB1_q_a[3]_PORT_B_data_in_reg = DFFE(YB1_q_a[3]_PORT_B_data_in, YB1_q_a[3]_clock_1, , , );
YB1_q_a[3]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[3]_PORT_A_address_reg = DFFE(YB1_q_a[3]_PORT_A_address, YB1_q_a[3]_clock_0, , , );
YB1_q_a[3]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[3]_PORT_B_address_reg = DFFE(YB1_q_a[3]_PORT_B_address, YB1_q_a[3]_clock_1, , , );
YB1_q_a[3]_PORT_A_write_enable = F1L02Q;
YB1_q_a[3]_PORT_A_write_enable_reg = DFFE(YB1_q_a[3]_PORT_A_write_enable, YB1_q_a[3]_clock_0, , , );
YB1_q_a[3]_PORT_B_write_enable = ZB1L83;
YB1_q_a[3]_PORT_B_write_enable_reg = DFFE(YB1_q_a[3]_PORT_B_write_enable, YB1_q_a[3]_clock_1, , , );
YB1_q_a[3]_clock_0 = E1_inst11;
YB1_q_a[3]_clock_1 = A1L51;
YB1_q_a[3]_PORT_A_data_out = MEMORY(YB1_q_a[3]_PORT_A_data_in_reg, YB1_q_a[3]_PORT_B_data_in_reg, YB1_q_a[3]_PORT_A_address_reg, YB1_q_a[3]_PORT_B_address_reg, YB1_q_a[3]_PORT_A_write_enable_reg, YB1_q_a[3]_PORT_B_write_enable_reg, , , YB1_q_a[3]_clock_0, YB1_q_a[3]_clock_1, , , , );
YB1_q_a[3] = YB1_q_a[3]_PORT_A_data_out[0];

--YB1_q_b[3] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[3]
YB1_q_b[3]_PORT_A_data_in = A1L09;
YB1_q_b[3]_PORT_A_data_in_reg = DFFE(YB1_q_b[3]_PORT_A_data_in, YB1_q_b[3]_clock_0, , , );
YB1_q_b[3]_PORT_B_data_in = ZB1_ram_rom_data_reg[3];
YB1_q_b[3]_PORT_B_data_in_reg = DFFE(YB1_q_b[3]_PORT_B_data_in, YB1_q_b[3]_clock_1, , , );
YB1_q_b[3]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[3]_PORT_A_address_reg = DFFE(YB1_q_b[3]_PORT_A_address, YB1_q_b[3]_clock_0, , , );
YB1_q_b[3]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[3]_PORT_B_address_reg = DFFE(YB1_q_b[3]_PORT_B_address, YB1_q_b[3]_clock_1, , , );
YB1_q_b[3]_PORT_A_write_enable = F1L02Q;
YB1_q_b[3]_PORT_A_write_enable_reg = DFFE(YB1_q_b[3]_PORT_A_write_enable, YB1_q_b[3]_clock_0, , , );
YB1_q_b[3]_PORT_B_write_enable = ZB1L83;
YB1_q_b[3]_PORT_B_write_enable_reg = DFFE(YB1_q_b[3]_PORT_B_write_enable, YB1_q_b[3]_clock_1, , , );
YB1_q_b[3]_clock_0 = E1_inst11;
YB1_q_b[3]_clock_1 = A1L51;
YB1_q_b[3]_PORT_B_data_out = MEMORY(YB1_q_b[3]_PORT_A_data_in_reg, YB1_q_b[3]_PORT_B_data_in_reg, YB1_q_b[3]_PORT_A_address_reg, YB1_q_b[3]_PORT_B_address_reg, YB1_q_b[3]_PORT_A_write_enable_reg, YB1_q_b[3]_PORT_B_write_enable_reg, , , YB1_q_b[3]_clock_0, YB1_q_b[3]_clock_1, , , , );
YB1_q_b[3] = YB1_q_b[3]_PORT_B_data_out[0];


--A1L88 is gdfx_temp0[3]~1354
--operation mode is normal

A1L88 = YB1_q_a[3] & (in[3] # !M1_q[15]) # !F1L59;


--H1_val[3] is trireg:inst7|val[3]
--operation mode is normal

H1_val[3]_lut_out = C1L43;
H1_val[3] = DFFEA(H1_val[3]_lut_out, inst20, VCC, , , , );


--A1L98 is gdfx_temp0[3]~1355
--operation mode is normal

A1L98 = M2_q[3] & (H1_val[3] # !F1_outRegRd) # !M2_q[3] & !F1L76 & (H1_val[3] # !F1_outRegRd);


--K1_ramdata[5][3] is regarray:inst10|ramdata[5][3]
--operation mode is normal

K1_ramdata[5][3]_lut_out = A1L09;
K1_ramdata[5][3] = DFFEA(K1_ramdata[5][3]_lut_out, inst11, VCC, , K1L6, , );


--K1_ramdata[6][3] is regarray:inst10|ramdata[6][3]
--operation mode is normal

K1_ramdata[6][3]_lut_out = A1L09;
K1_ramdata[6][3] = DFFEA(K1_ramdata[6][3]_lut_out, inst11, VCC, , K1L7, , );


--K1_ramdata[4][3] is regarray:inst10|ramdata[4][3]
--operation mode is normal

K1_ramdata[4][3]_lut_out = A1L09;
K1_ramdata[4][3] = DFFEA(K1_ramdata[4][3]_lut_out, inst11, VCC, , K1L5, , );


--K1L261 is regarray:inst10|temp_data[3]~66
--operation mode is normal

K1L261 = F1L58 & (F1L18 # K1_ramdata[6][3]) # !F1L58 & !F1L18 & K1_ramdata[4][3];


--K1_ramdata[7][3] is regarray:inst10|ramdata[7][3]
--operation mode is normal

K1_ramdata[7][3]_lut_out = A1L09;
K1_ramdata[7][3] = DFFEA(K1_ramdata[7][3]_lut_out, inst11, VCC, , K1L8, , );


--K1L361 is regarray:inst10|temp_data[3]~67
--operation mode is normal

K1L361 = K1L261 & (K1_ramdata[7][3] # !F1L18) # !K1L261 & K1_ramdata[5][3] & F1L18;


--K1_ramdata[2][3] is regarray:inst10|ramdata[2][3]
--operation mode is normal

K1_ramdata[2][3]_lut_out = A1L09;
K1_ramdata[2][3] = DFFEA(K1_ramdata[2][3]_lut_out, inst11, VCC, , K1L3, , );


--K1_ramdata[1][3] is regarray:inst10|ramdata[1][3]
--operation mode is normal

K1_ramdata[1][3]_lut_out = A1L09;
K1_ramdata[1][3] = DFFEA(K1_ramdata[1][3]_lut_out, inst11, VCC, , K1L2, , );


--K1_ramdata[0][3] is regarray:inst10|ramdata[0][3]
--operation mode is normal

K1_ramdata[0][3]_lut_out = A1L09;
K1_ramdata[0][3] = DFFEA(K1_ramdata[0][3]_lut_out, inst11, VCC, , K1L1, , );


--K1L061 is regarray:inst10|temp_data[3]~64
--operation mode is normal

K1L061 = F1L18 & (F1L58 # K1_ramdata[1][3]) # !F1L18 & !F1L58 & K1_ramdata[0][3];


--K1_ramdata[3][3] is regarray:inst10|ramdata[3][3]
--operation mode is normal

K1_ramdata[3][3]_lut_out = A1L09;
K1_ramdata[3][3] = DFFEA(K1_ramdata[3][3]_lut_out, inst11, VCC, , K1L4, , );


--K1L161 is regarray:inst10|temp_data[3]~65
--operation mode is normal

K1L161 = K1L061 & (K1_ramdata[3][3] # !F1L58) # !K1L061 & K1_ramdata[2][3] & F1L58;


--K1L461 is regarray:inst10|temp_data[3]~3040
--operation mode is normal

K1L461 = F1L68 & K1L361 # !F1L68 & (F1L98 & K1L361 # !F1L98 & K1L161);


--A1L09 is gdfx_temp0[3]~1356
--operation mode is normal

A1L09 = A1L88 & A1L98 & (K1L461 # !F1L67);


--D1L3 is comp:inst1|compout~264
--operation mode is normal

D1L3 = M3_q[3] & A1L09 & (M3_q[9] $ !A1L011) # !M3_q[3] & !A1L09 & (M3_q[9] $ !A1L011);


--M3_q[14] is reg_l:inst21|q[14]
--operation mode is normal

M3_q[14]_lut_out = A1L031;
M3_q[14] = DFFEA(M3_q[14]_lut_out, E1_inst11, !RST, , F1L43Q, , );


--YB1_q_a[14] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 16, Port B Logical Depth: 128, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_a[14]_PORT_A_data_in = A1L031;
YB1_q_a[14]_PORT_A_data_in_reg = DFFE(YB1_q_a[14]_PORT_A_data_in, YB1_q_a[14]_clock_0, , , );
YB1_q_a[14]_PORT_B_data_in = ZB1_ram_rom_data_reg[14];
YB1_q_a[14]_PORT_B_data_in_reg = DFFE(YB1_q_a[14]_PORT_B_data_in, YB1_q_a[14]_clock_1, , , );
YB1_q_a[14]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_a[14]_PORT_A_address_reg = DFFE(YB1_q_a[14]_PORT_A_address, YB1_q_a[14]_clock_0, , , );
YB1_q_a[14]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_a[14]_PORT_B_address_reg = DFFE(YB1_q_a[14]_PORT_B_address, YB1_q_a[14]_clock_1, , , );
YB1_q_a[14]_PORT_A_write_enable = F1L02Q;
YB1_q_a[14]_PORT_A_write_enable_reg = DFFE(YB1_q_a[14]_PORT_A_write_enable, YB1_q_a[14]_clock_0, , , );
YB1_q_a[14]_PORT_B_write_enable = ZB1L83;
YB1_q_a[14]_PORT_B_write_enable_reg = DFFE(YB1_q_a[14]_PORT_B_write_enable, YB1_q_a[14]_clock_1, , , );
YB1_q_a[14]_clock_0 = E1_inst11;
YB1_q_a[14]_clock_1 = A1L51;
YB1_q_a[14]_PORT_A_data_out = MEMORY(YB1_q_a[14]_PORT_A_data_in_reg, YB1_q_a[14]_PORT_B_data_in_reg, YB1_q_a[14]_PORT_A_address_reg, YB1_q_a[14]_PORT_B_address_reg, YB1_q_a[14]_PORT_A_write_enable_reg, YB1_q_a[14]_PORT_B_write_enable_reg, , , YB1_q_a[14]_clock_0, YB1_q_a[14]_clock_1, , , , );
YB1_q_a[14] = YB1_q_a[14]_PORT_A_data_out[0];

--YB1_q_b[14] is ram_a:inst18|altsyncram:altsyncram_component|altsyncram_5n21:auto_generated|altsyncram_7gd2:altsyncram1|q_b[14]
YB1_q_b[14]_PORT_A_data_in = A1L031;
YB1_q_b[14]_PORT_A_data_in_reg = DFFE(YB1_q_b[14]_PORT_A_data_in, YB1_q_b[14]_clock_0, , , );
YB1_q_b[14]_PORT_B_data_in = ZB1_ram_rom_data_reg[14];
YB1_q_b[14]_PORT_B_data_in_reg = DFFE(YB1_q_b[14]_PORT_B_data_in, YB1_q_b[14]_clock_1, , , );
YB1_q_b[14]_PORT_A_address = BUS(M1_q[0], M1_q[1], M1_q[2], M1_q[3], M1_q[4], M1_q[5], M1_q[6]);
YB1_q_b[14]_PORT_A_address_reg = DFFE(YB1_q_b[14]_PORT_A_address, YB1_q_b[14]_clock_0, , , );
YB1_q_b[14]_PORT_B_address = BUS(AC1_safe_q[0], AC1_safe_q[1], AC1_safe_q[2], AC1_safe_q[3], AC1_safe_q[4], AC1_safe_q[5], AC1_safe_q[6]);
YB1_q_b[14]_PORT_B_address_reg = DFFE(YB1_q_b[14]_PORT_B_address, YB1_q_b[14]_clock_1, , , );
YB1_q_b[14]_PORT_A_write_enable = F1L02Q;
YB1_q_b[14]_PORT_A_write_enable_reg = DFFE(YB1_q_b[14]_PORT_A_write_enable, YB1_q_b[14]_clock_0, , , );
YB1_q_b[14]_PORT_B_write_enable = ZB1L83;
YB1_q_b[14]_PORT_B_write_enable_reg = DFFE(YB1_q_b[14]_PORT_B_write_enable, YB1_q_b[14]_clock_1, , , );
YB1_q_b[14]_clock_0 = E1_inst11;
YB1_q_b[14]_clock_1 = A1L51;
YB1_q_b[14]_PORT_B_data_out = MEMORY(YB1_q_b[14]_PORT_A_data_in_reg, YB1_q_b[14]_PORT_B_data_in_reg, YB1_q_b[14]_PORT_A_address_reg, YB1_q_b[14]_PORT_B_address_reg, YB1_q_b[14]_PORT_A_write_enable_reg, YB1_q_b[14]_PORT_B_write_enable_reg, , , YB1_q_b[14]_clock_0, YB1_q_b[14]_clock_1, , , , );
YB1_q_b[14] = YB1_q_b[14]_PORT_B_data_out[0];


--A1L721 is gdfx_temp0[14]~1357
--operation mode is normal

A1L721 = YB1_q_a[14] & (in[14] # !M1_q[15]) # !F1L59;


--M2_q[14] is reg_l:inst17|q[14]
--operation mode is normal

M2_q[14]_lut_out = A1L031;
M2_q[14] = DFFEA(M2_q[14]_lut_out, E1_inst8, !RST, , F1L07, , );


--H1_val[14] is trireg:inst7|val[14]
--operation mode is normal

H1_val[14]_lut_out = C1L73;
H1_val[14] = DFFEA(H1_val[14]_lut_out, inst20, VCC, , , , );


--A1L821 is gdfx_temp0[14]~1358
--operation mode is normal

A1L821 = M2_q[14] & (H1_val[14] # !F1_outRegRd) # !M2_q[14] & !F1L76 & (H1_val[14] # !F1_outRegRd);


--K1_ramdata[2][14] is regarray:inst10|ramdata[2][14]
--operation mode is normal

K1_ramdata[2][14]_lut_out = A1L031;
K1_ramdata[2][14] = DFFEA(K1_ramdata[2][14]_lut_out, inst11, VCC, , K1L3, , );


--K1_ramdata[1][14] is regarray:inst10|ramdata[1][14]
--operation mode is normal

K1_ramdata[1][14]_lut_out = A1L031;
K1_ramdata[1][14] = DFFEA(K1_ramdata[1][14]_lut_out, inst11, VCC, , K1L2, , );


--K1_ramdata[0][14] is regarray:inst10|ramdata[0][14]
--operation mode is normal

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