# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		ZongHe_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:38:42  MAY 04, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VERILOG_FILE ZongHe.v

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY ZongHe

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7128SLC84-10"
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL

# Assembler Assignments
# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

set_location_assignment PIN_83 -to ClkIn
set_location_assignment PIN_69 -to DAddin
set_location_assignment PIN_67 -to DAddout
set_location_assignment PIN_56 -to Din0
set_location_assignment PIN_61 -to Din1
set_location_assignment PIN_64 -to Din2
set_location_assignment PIN_73 -to Dout0
set_location_assignment PIN_74 -to Dout1
set_location_assignment PIN_75 -to Dout2
set_location_assignment PIN_76 -to count8
set_location_assignment PIN_80 -to count2048
set_location_assignment PIN_62 -to TCK
set_location_assignment PIN_14 -to TDI
set_location_assignment PIN_71 -to TDO
set_location_assignment PIN_23 -to TMS
set_location_assignment PIN_77 -to count64