; N/A   ; None              ; 10.000 ns       ; Din1   ; DAddout ;
; N/A   ; None              ; 10.000 ns       ; DAddin ; Dout1   ;
; N/A   ; None              ; 10.000 ns       ; Din0   ; Dout0   ;
+-------+-------------------+-----------------+--------+---------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+--------+----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To             ; To Clock ;
+---------------+-------------+-----------+--------+----------------+----------+
; N/A           ; None        ; 6.000 ns  ; DAddin ; DataBufIn1[0]  ; ClkIn    ;
; N/A           ; None        ; 6.000 ns  ; Din2   ; DataBufOut1[0] ; ClkIn    ;
+---------------+-------------+-----------+--------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jun 01 22:41:21 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ZongHe -c ZongHe
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "ClkIn" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "count[9]" as buffer
    Info: Detected ripple clock "count[5]" as buffer
    Info: Detected ripple clock "count[4]" as buffer
    Info: Detected ripple clock "count[1]" as buffer
Info: Clock "ClkIn" has Internal fmax of 100.0 MHz between source register "count[0]" and destination register "count[0]" (period= 10.0 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC33; Fanout = 11; REG Node = 'count[0]'
        Info: 2: + IC(0.000 ns) + CELL(6.000 ns) = 6.000 ns; Loc. = LC33; Fanout = 11; REG Node = 'count[0]'
        Info: Total cell delay = 6.000 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "ClkIn" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC33; Fanout = 11; REG Node = 'count[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "ClkIn" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC33; Fanout = 11; REG Node = 'count[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "ClkIn" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "count[9]" and destination pin or register "DataBufIn1[0]" for clock "ClkIn" (Hold time is 3.0 ns)
    Info: + Largest clock skew is 8.000 ns
        Info: + Longest clock path from clock "ClkIn" to destination register is 9.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'
            Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC113; Fanout = 38; REG Node = 'count[5]'
            Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1[0]'
            Info: Total cell delay = 8.500 ns ( 89.47 % )
            Info: Total interconnect delay = 1.000 ns ( 10.53 % )
        Info: - Shortest clock path from clock "ClkIn" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC116; Fanout = 8; REG Node = 'count[9]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: - Micro clock to output delay of source is 2.000 ns
    Info: - Shortest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC116; Fanout = 8; REG Node = 'count[9]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1[0]'
        Info: Total cell delay = 5.000 ns ( 83.33 % )
        Info: Total interconnect delay = 1.000 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 3.000 ns
Info: tsu for register "DataBufIn1[0]" (data pin = "DAddin", clock pin = "ClkIn") is -1.000 ns
    Info: + Longest pin to register delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_69; Fanout = 2; PIN Node = 'DAddin'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1[0]'
        Info: Total cell delay = 5.500 ns ( 84.62 % )
        Info: Total interconnect delay = 1.000 ns ( 15.38 % )
    Info: + Micro setup delay of destination is 2.000 ns
    Info: - Shortest clock path from clock "ClkIn" to destination register is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'
        Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC113; Fanout = 38; REG Node = 'count[5]'
        Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1[0]'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
Info: tco from clock "ClkIn" to destination pin "Dout2" through register "DataBufIn1[23]" is 21.000 ns
    Info: + Longest clock path from clock "ClkIn" to source register is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'
        Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC113; Fanout = 38; REG Node = 'count[5]'
        Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC3; Fanout = 1; REG Node = 'DataBufIn1[23]'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'DataBufIn1[23]'
        Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC118; Fanout = 1; COMB Node = 'Dout2~12'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'Dout2'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
Info: Longest tpd from source pin "Din1" to destination pin "DAddout" is 10.000 ns
    Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_61; Fanout = 1; PIN Node = 'Din1'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC104; Fanout = 1; COMB Node = 'DAddout~18'
    Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'DAddout'
    Info: Total cell delay = 9.000 ns ( 90.00 % )
    Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: th for register "DataBufIn1[0]" (data pin = "DAddin", clock pin = "ClkIn") is 6.000 ns
    Info: + Longest clock path from clock "ClkIn" to destination register is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'
        Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC113; Fanout = 38; REG Node = 'count[5]'
        Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1[0]'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
    Info: + Micro hold delay of destination is 3.000 ns
    Info: - Shortest pin to register delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_69; Fanout = 2; PIN Node = 'DAddin'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1[0]'
        Info: Total cell delay = 5.500 ns ( 84.62 % )
        Info: Total interconnect delay = 1.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Processing ended: Fri Jun 01 22:41:22 2007
    Info: Elapsed time: 00:00:01