{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 01 22:41:10 2007 " "Info: Processing started: Fri Jun 01 22:41:10 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ZongHe -c ZongHe " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ZongHe -c ZongHe" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ZongHe.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ZongHe.v" { { "Info" "ISGN_ENTITY_NAME" "1 ZongHe " "Info: Found entity 1: ZongHe" {  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ZongHe " "Info: Elaborating entity \"ZongHe\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 ZongHe.v(31) " "Warning (10230): Verilog HDL assignment warning at ZongHe.v(31): truncated value with size 32 to match size of target (16)" {  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 31 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ZongHe.v(71) " "Warning (10230): Verilog HDL assignment warning at ZongHe.v(71): truncated value with size 32 to match size of target (1)" {  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ZongHe.v(75) " "Warning (10230): Verilog HDL assignment warning at ZongHe.v(75): truncated value with size 32 to match size of target (1)" {  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ZongHe.v(76) " "Warning (10230): Verilog HDL assignment warning at ZongHe.v(76): truncated value with size 32 to match size of target (1)" {  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ZongHe.v(77) " "Warning (10230): Verilog HDL assignment warning at ZongHe.v(77): truncated value with size 32 to match size of target (1)" {  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 31 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[1\] lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[1\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 276 9 0 } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 31 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 16 " "Info: Parameter \"LPM_WIDTH\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 31 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 31 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}