?? zonghe.tan.qmsg
字號:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "ClkIn " "Info: Assuming node \"ClkIn\" is an undefined clock" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 4 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ClkIn" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "count\[9\] " "Info: Detected ripple clock \"count\[9\]\" as buffer" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count\[5\] " "Info: Detected ripple clock \"count\[5\]\" as buffer" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count\[4\] " "Info: Detected ripple clock \"count\[4\]\" as buffer" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count\[1\] " "Info: Detected ripple clock \"count\[1\]\" as buffer" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "ClkIn register count\[0\] register count\[0\] 100.0 MHz 10.0 ns Internal " "Info: Clock \"ClkIn\" has Internal fmax of 100.0 MHz between source register \"count\[0\]\" and destination register \"count\[0\]\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LC33 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC33; Fanout = 11; REG Node = 'count\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 6.000 ns count\[0\] 2 REG LC33 11 " "Info: 2: + IC(0.000 ns) + CELL(6.000 ns) = 6.000 ns; Loc. = LC33; Fanout = 11; REG Node = 'count\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[0] count[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 100.00 % ) " "Info: Total cell delay = 6.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[0] count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.000 ns" { count[0] count[0] } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"ClkIn\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns ClkIn 1 CLK PIN_83 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns count\[0\] 2 REG LC33 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC33; Fanout = 11; REG Node = 'count\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { ClkIn count[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"ClkIn\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns ClkIn 1 CLK PIN_83 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns count\[0\] 2 REG LC33 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC33; Fanout = 11; REG Node = 'count\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { ClkIn count[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[0] count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.000 ns" { count[0] count[0] } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "ClkIn 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"ClkIn\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "count\[9\] DataBufIn1\[0\] ClkIn 3.0 ns " "Info: Found hold time violation between source pin or register \"count\[9\]\" and destination pin or register \"DataBufIn1\[0\]\" for clock \"ClkIn\" (Hold time is 3.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.000 ns + Largest " "Info: + Largest clock skew is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn destination 9.500 ns + Longest register " "Info: + Longest clock path from clock \"ClkIn\" to destination register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns ClkIn 1 CLK PIN_83 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns count\[5\] 2 REG LC113 38 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC113; Fanout = 38; REG Node = 'count\[5\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { ClkIn count[5] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns DataBufIn1\[0\] 3 REG LC122 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[5] DataBufIn1[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.500 ns" { ClkIn count[5] DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.500 ns" { ClkIn ClkIn~out count[5] DataBufIn1[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn source 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"ClkIn\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns ClkIn 1 CLK PIN_83 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns count\[9\] 2 REG LC116 8 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC116; Fanout = 8; REG Node = 'count\[9\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { ClkIn count[9] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.500 ns" { ClkIn count[5] DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.500 ns" { ClkIn ClkIn~out count[5] DataBufIn1[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Shortest register register " "Info: - Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[9\] 1 REG LC116 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC116; Fanout = 8; REG Node = 'count\[9\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count[9] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns DataBufIn1\[0\] 2 REG LC122 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[9] DataBufIn1[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[9] DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.000 ns" { count[9] DataBufIn1[0] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 68 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.500 ns" { ClkIn count[5] DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.500 ns" { ClkIn ClkIn~out count[5] DataBufIn1[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ClkIn count[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { ClkIn ClkIn~out count[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[9] DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.000 ns" { count[9] DataBufIn1[0] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "DataBufIn1\[0\] DAddin ClkIn -1.000 ns register " "Info: tsu for register \"DataBufIn1\[0\]\" (data pin = \"DAddin\", clock pin = \"ClkIn\") is -1.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DAddin 1 PIN PIN_69 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_69; Fanout = 2; PIN Node = 'DAddin'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DAddin } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns DataBufIn1\[0\] 2 REG LC122 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { DAddin DataBufIn1[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { DAddin DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { DAddin DAddin~out DataBufIn1[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 68 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn destination 9.500 ns - Shortest register " "Info: - Shortest clock path from clock \"ClkIn\" to destination register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns ClkIn 1 CLK PIN_83 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 11; CLK Node = 'ClkIn'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns count\[5\] 2 REG LC113 38 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC113; Fanout = 38; REG Node = 'count\[5\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { ClkIn count[5] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns DataBufIn1\[0\] 3 REG LC122 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC122; Fanout = 1; REG Node = 'DataBufIn1\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { count[5] DataBufIn1[0] } "NODE_NAME" } } { "ZongHe.v" "" { Text "E:/SXF/ZongHe(07-06-01)/ZongHe.v" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.500 ns" { ClkIn count[5] DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.500 ns" { ClkIn ClkIn~out count[5] DataBufIn1[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { DAddin DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { DAddin DAddin~out DataBufIn1[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.500 ns" { ClkIn count[5] DataBufIn1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.500 ns" { ClkIn ClkIn~out count[5] DataBufIn1[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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