`timescale 1ns/1ns                                                             
                                                                               
module Ham_Code_T (clk, rst, ,ack, datain, cout, dataout, req);                      
                                                                               
//input	signal                                                                 
input 		clk,rst;                                                       
input		ack;                                                           
input	[3:0]	datain;                                                        
                                                                               
//output signal                                                                
output	[3:0]	dataout;                                                     
output		req;                                                           
                                                                               
wire	[3:0]	dataout;                                                     
wire		req;                                                           
                                                                               
                                                   
                                                                               
reg		h1,h2,h3,h4,h5,h6,h7;                                          

wire 		c1 = datain[3] ^ datain [2] ^ datain [0];
wire		c2 = datain[3] ^ datain [1] ^ datain [0];
wire		c3 = datain[2] ^ datain [1] ^ datain [0];


assign 		cout = {c1,c2,c3};
                                                                               
always @(posedge clk or negedge rst)begin                                      
	if (~rst)                                                              
		begin                                                          
		h1 <= 'bx;                                                     
		h2 <= 'bx;                                                     
		h3 <= 'bx;                                                     
		h4 <= 'bx;                                                     
		h5 <= 'bx;                                                     
		h6 <= 'bx;                                                     
		h7 <= 'bx;                                                     
		end                                                            
	else                           
		begin                                        
	        {h1,h2,h3,h4,h5,h6,h7} = (ack)? {t1,t2,datain[3],t3,datain[2],datain[1],datain[0]}: 7'bx;                                           
		end                                                            
end                                                                            
                                                                               
//**********************************************************                   
//			req                                                    
//**********************************************************                   
                                                                               
reg	reqs;                                                                  
                                                                               
always @(posedge clk or negedge rst)begin                                      
	if  (~rst)                                                             
	reqs <= 1'b1;                                                          
	else                                                                   
	reqs <= ~ack;                                                          
end                                                                            
                                                                               
assign req = reqs;                                                             
                                                                               
assign dataout = {h3,h5,h6,h7};                                     
                                                                               
endmodule