<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (LVTTL|SSTL3_I|LVCMOS33|LVCMOS25|SSTL2_I|LVCMOS18|LVCMOS15|HSTL_I|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW"
  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="CP56" spg="-6" arch="xbr" device="XC2C32A"/><pin nm="clk" no="J1" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;0&gt;" no="C4" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;1&gt;" no="C5" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;2&gt;" no="C8" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;3&gt;" no="A10" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;4&gt;" no="B10" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;5&gt;" no="C10" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;6&gt;" no="E8" dir="input" iostd="LVCMOS18"/><pin nm="column&lt;7&gt;" no="K2" dir="input" iostd="LVCMOS18"/><pin nm="out&lt;0&gt;" no="A1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="out&lt;1&gt;" no="G1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="out&lt;2&gt;" no="F3" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="out&lt;3&gt;" no="H1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="out&lt;4&gt;" no="G3" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="out&lt;5&gt;" no="K1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;0&gt;" no="F1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;1&gt;" no="E3" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;2&gt;" no="E1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;3&gt;" no="D1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;4&gt;" no="C1" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;5&gt;" no="A3" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;6&gt;" no="A2" sr="fast" dir="output" iostd="LVCMOS18"/><pin nm="row&lt;7&gt;" no="B1" sr="fast" dir="output" iostd="LVCMOS18"/></ibis>