Release 6.3.03i - netgen G.38Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.Reading design KeypadScan.nga ...  Flattening design ...  Flattening design completed.  Specializing design ...  Specializing design completed.  Preping physical only global signals ...  Preping design's networks ...  Preping design's macros ...Writing Verilog SDF file KeypadScan_timesim.sdf ...Writing Verilog netlist file KeypadScan_timesim.v ...INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Simulation Design Guide:
   http://support.xilinx.com/support/software_manuals.htm Total memory usage is 34504 kilobytes