LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adder8 IS
PORT(
		cin		: IN	STD_LOGIC;						--進位輸入
        a,b     : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);	--加數(shù)
		s   	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--和
        cout    : OUT   STD_LOGIC);						--進位輸出
END adder8;
ARCHITECTURE rtl OF adder8 IS
	COMPONENT adder									    --元件聲明，引用5.2中給出的一位全加器
		PORT(
		a,b,cin		: IN	STD_LOGIC;
		s,cout		: OUT	STD_LOGIC);
	END COMPONENT;
    SIGNAL cout_temp  : STD_LOGIC_VECTOR(7 DOWNTO 0);   --每個一位全加器的進位輸出
BEGIN
       g1: FOR i IN 1 TO 7 GENERATE						--實例化元件
               adder_portmap: adder PORT MAP(a(i),b(i),cout_temp(i-1),s(i),cout_temp(i));
           END GENERATE; 
	   adder0_map: adder PORT MAP(a(0),b(0),cin,s(0),cout_temp(0));
          cout<=cout_temp(7);
END rtl;