?? elec_lock.fit.eqn

?? 本程序是用VHDL語言實現電子密碼鎖功能,整個系統分為三大模塊,一為控制模塊,二為鍵盤顯示模塊,三為處理模塊
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--operation mode is normal

A1L151Q = REG[1];


--REG[4] is REG[4] at LC4_A18
--operation mode is normal

REG[4]_lut_out = ACC[4];
REG[4] = DFFEA(REG[4]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L157Q is REG[4]~44 at LC4_A18
--operation mode is normal

A1L157Q = REG[4];


--A1L196 is rtl~553 at LC8_A24
--operation mode is normal

A1L196 = (REG[4] & ACC[4] & (REG[1] $ !ACC[1]) # !REG[4] & !ACC[4] & (REG[1] $ !ACC[1])) & CASCADE(A1L211);

--A1L212 is rtl~575 at LC8_A24
--operation mode is normal

A1L212 = (REG[4] & ACC[4] & (REG[1] $ !ACC[1]) # !REG[4] & !ACC[4] & (REG[1] $ !ACC[1])) & CASCADE(A1L211);


--REG[10] is REG[10] at LC5_A17
--operation mode is normal

REG[10]_lut_out = ACC[10];
REG[10] = DFFEA(REG[10]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L169Q is REG[10]~45 at LC5_A17
--operation mode is normal

A1L169Q = REG[10];


--REG[11] is REG[11] at LC8_A17
--operation mode is normal

REG[11]_lut_out = ACC[11];
REG[11] = DFFEA(REG[11]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L171Q is REG[11]~46 at LC8_A17
--operation mode is normal

A1L171Q = REG[11];


--A1L191 is rtl~543 at LC1_A17
--operation mode is normal

A1L191 = REG[11] & ACC[11] & (REG[10] $ !ACC[10]) # !REG[11] & !ACC[11] & (REG[10] $ !ACC[10]);

--A1L213 is rtl~576 at LC1_A17
--operation mode is normal

A1L213 = REG[11] & ACC[11] & (REG[10] $ !ACC[10]) # !REG[11] & !ACC[11] & (REG[10] $ !ACC[10]);

--A1L214 is rtl~577 at LC1_A17
--operation mode is normal

A1L214 = REG[11] & ACC[11] & (REG[10] $ !ACC[10]) # !REG[11] & !ACC[11] & (REG[10] $ !ACC[10]);


--REG[0] is REG[0] at LC2_A18
--operation mode is normal

REG[0]_lut_out = ACC[0];
REG[0] = DFFEA(REG[0]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L148Q is REG[0]~47 at LC2_A18
--operation mode is normal

A1L148Q = REG[0];


--REG[2] is REG[2] at LC2_A20
--operation mode is normal

REG[2]_lut_out = ACC[2];
REG[2] = DFFEA(REG[2]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L153Q is REG[2]~48 at LC2_A20
--operation mode is normal

A1L153Q = REG[2];


--A1L197 is rtl~554 at LC2_A17
--operation mode is normal

A1L197 = (REG[2] & ACC[2] & (REG[0] $ !ACC[0]) # !REG[2] & !ACC[2] & (REG[0] $ !ACC[0])) & CASCADE(A1L214);

--A1L215 is rtl~578 at LC2_A17
--operation mode is normal

A1L215 = (REG[2] & ACC[2] & (REG[0] $ !ACC[0]) # !REG[2] & !ACC[2] & (REG[0] $ !ACC[0])) & CASCADE(A1L214);


--REG[15] is REG[15] at LC3_A14
--operation mode is normal

REG[15]_lut_out = ACC[15];
REG[15] = DFFEA(REG[15]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L179Q is REG[15]~49 at LC3_A14
--operation mode is normal

A1L179Q = REG[15];


--REG[3] is REG[3] at LC4_A14
--operation mode is normal

REG[3]_lut_out = ACC[3];
REG[3] = DFFEA(REG[3]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L155Q is REG[3]~50 at LC4_A14
--operation mode is normal

A1L155Q = REG[3];


--A1L192 is rtl~545 at LC7_A14
--operation mode is normal

A1L192 = REG[3] & ACC[3] & (REG[15] $ !ACC[15]) # !REG[3] & !ACC[3] & (REG[15] $ !ACC[15]);

--A1L216 is rtl~579 at LC7_A14
--operation mode is normal

A1L216 = REG[3] & ACC[3] & (REG[15] $ !ACC[15]) # !REG[3] & !ACC[3] & (REG[15] $ !ACC[15]);

--A1L217 is rtl~580 at LC7_A14
--operation mode is normal

A1L217 = REG[3] & ACC[3] & (REG[15] $ !ACC[15]) # !REG[3] & !ACC[3] & (REG[15] $ !ACC[15]);


--REG[5] is REG[5] at LC6_A14
--operation mode is normal

REG[5]_lut_out = ACC[5];
REG[5] = DFFEA(REG[5]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L159Q is REG[5]~51 at LC6_A14
--operation mode is normal

A1L159Q = REG[5];


--REG[12] is REG[12] at LC5_A18
--operation mode is normal

REG[12]_lut_out = ACC[12];
REG[12] = DFFEA(REG[12]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L173Q is REG[12]~52 at LC5_A18
--operation mode is normal

A1L173Q = REG[12];


--A1L198 is rtl~555 at LC8_A14
--operation mode is normal

A1L198 = (REG[12] & ACC[12] & (REG[5] $ !ACC[5]) # !REG[12] & !ACC[12] & (REG[5] $ !ACC[5])) & CASCADE(A1L217);

--A1L218 is rtl~581 at LC8_A14
--operation mode is normal

A1L218 = (REG[12] & ACC[12] & (REG[5] $ !ACC[5]) # !REG[12] & !ACC[12] & (REG[5] $ !ACC[5])) & CASCADE(A1L217);


--REG[6] is REG[6] at LC3_A15
--operation mode is normal

REG[6]_lut_out = ACC[6];
REG[6] = DFFEA(REG[6]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L161Q is REG[6]~53 at LC3_A15
--operation mode is normal

A1L161Q = REG[6];


--REG[14] is REG[14] at LC4_A15
--operation mode is normal

REG[14]_lut_out = ACC[14];
REG[14] = DFFEA(REG[14]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L177Q is REG[14]~54 at LC4_A15
--operation mode is normal

A1L177Q = REG[14];


--A1L193 is rtl~547 at LC1_A15
--operation mode is normal

A1L193 = REG[14] & ACC[14] & (REG[6] $ !ACC[6]) # !REG[14] & !ACC[14] & (REG[6] $ !ACC[6]);

--A1L219 is rtl~582 at LC1_A15
--operation mode is normal

A1L219 = REG[14] & ACC[14] & (REG[6] $ !ACC[6]) # !REG[14] & !ACC[14] & (REG[6] $ !ACC[6]);

--A1L220 is rtl~583 at LC1_A15
--operation mode is normal

A1L220 = REG[14] & ACC[14] & (REG[6] $ !ACC[6]) # !REG[14] & !ACC[14] & (REG[6] $ !ACC[6]);


--REG[7] is REG[7] at LC6_A15
--operation mode is normal

REG[7]_lut_out = ACC[7];
REG[7] = DFFEA(REG[7]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L163Q is REG[7]~55 at LC6_A15
--operation mode is normal

A1L163Q = REG[7];


--REG[13] is REG[13] at LC7_A15
--operation mode is normal

REG[13]_lut_out = ACC[13];
REG[13] = DFFEA(REG[13]_lut_out, GLOBAL(D1_q[0]), , , A1L147, , );

--A1L175Q is REG[13]~56 at LC7_A15
--operation mode is normal

A1L175Q = REG[13];


--A1L199 is rtl~556 at LC2_A15
--operation mode is normal

A1L199 = (REG[13] & ACC[13] & (REG[7] $ !ACC[7]) # !REG[13] & !ACC[13] & (REG[7] $ !ACC[7])) & CASCADE(A1L220);

--A1L221 is rtl~584 at LC2_A15
--operation mode is normal

A1L221 = (REG[13] & ACC[13] & (REG[7] $ !ACC[7]) # !REG[13] & !ACC[13] & (REG[7] $ !ACC[7])) & CASCADE(A1L220);


--A1L194 is rtl~549 at LC6_A13
--operation mode is normal

A1L194 = !ACC[6] & !ACC[5] & !ACC[4] & ACC[7];

--A1L222 is rtl~585 at LC6_A13
--operation mode is normal

A1L222 = !ACC[6] & !ACC[5] & !ACC[4] & ACC[7];

--A1L223 is rtl~586 at LC6_A13
--operation mode is normal

A1L223 = !ACC[6] & !ACC[5] & !ACC[4] & ACC[7];


--A1L200 is rtl~557 at LC7_A13
--operation mode is normal

A1L200 = (!ACC[3] & !ACC[2] & !ACC[1] & !ACC[0]) & CASCADE(A1L223);

--A1L224 is rtl~587 at LC7_A13
--operation mode is normal

A1L224 = (!ACC[3] & !ACC[2] & !ACC[1] & !ACC[0]) & CASCADE(A1L223);


--A1L195 is rtl~551 at LC3_A16
--operation mode is normal

A1L195 = !ACC[15] & !ACC[14] & !ACC[12] & ACC[13];

--A1L225 is rtl~588 at LC3_A16
--operation mode is normal

A1L225 = !ACC[15] & !ACC[14] & !ACC[12] & ACC[13];

--A1L226 is rtl~589 at LC3_A16
--operation mode is normal

A1L226 = !ACC[15] & !ACC[14] & !ACC[12] & ACC[13];


--A1L201 is rtl~558 at LC4_A16
--operation mode is normal

A1L201 = (!ACC[11] & !ACC[9] & ACC[10] & ACC[8]) & CASCADE(A1L226);

--A1L227 is rtl~590 at LC4_A16
--operation mode is normal

A1L227 = (!ACC[11] & !ACC[9] & ACC[10] & ACC[8]) & CASCADE(A1L226);


--A1L147 is REG[0]~15 at LC1_A13
--operation mode is normal

A1L147 = A1L189 & F[2];

--A1L149 is REG[0]~57 at LC1_A13
--operation mode is normal

A1L149 = A1L189 & F[2];


--A1L128 is NC[0]~1 at LC6_A19
--operation mode is normal

A1L128 = !NC[2];

--A1L130 is NC[0]~7 at LC6_A19
--operation mode is normal

A1L130 = !NC[2];


--CLK_4M is CLK_4M at PIN_43
--operation mode is input

CLK_4M = INPUT();


--KEY_IN[1] is KEY_IN[1] at PIN_84
--operation mode is input

KEY_IN[1] = INPUT();


--KEY_IN[0] is KEY_IN[0] at PIN_2
--operation mode is input

KEY_IN[0] = INPUT();


--KEY_IN[2] is KEY_IN[2] at PIN_44
--operation mode is input

KEY_IN[2] = INPUT();


--CLK_SCAN[0] is CLK_SCAN[0] at PIN_21
--operation mode is output

CLK_SCAN[0] = OUTPUT(A1L182);


--CLK_SCAN[1] is CLK_SCAN[1] at PIN_9
--operation mode is output

CLK_SCAN[1] = OUTPUT(!A1L186);


--CLK_SCAN[2] is CLK_SCAN[2] at PIN_23
--operation mode is output

CLK_SCAN[2] = OUTPUT(!A1L183);


--CLK_SCAN[3] is CLK_SCAN[3] at PIN_10
--operation mode is output

CLK_SCAN[3] = OUTPUT(!A1L261);


--FLAG_NUMB is FLAG_NUMB at PIN_71
--operation mode is output

FLAG_NUMB = OUTPUT(A1L92);


--FLAG_FUNC is FLAG_FUNC at PIN_73
--operation mode is output

FLAG_FUNC = OUTPUT(A1L88);


--LED_COM is LED_COM at PIN_38
--operation mode is output

LED_COM = OUTPUT(VCC);


--CLEAR is CLEAR at PIN_62
--operation mode is output

CLEAR = OUTPUT(A1L180);


--ENLOCK is ENLOCK at PIN_83
--operation mode is output

ENLOCK = OUTPUT(A1L79);


--NUMB_CNT[0] is NUMB_CNT[0] at PIN_22
--operation mode is output

NUMB_CNT[0] = OUTPUT(NC[0]);


--NUMB_CNT[1] is NUMB_CNT[1] at PIN_66
--operation mode is output

NUMB_CNT[1] = OUTPUT(NC[1]);


--NUMB_CNT[2] is NUMB_CNT[2] at PIN_70
--operation mode is output

NUMB_CNT[2] = OUTPUT(NC[2]);


--BCD_CODE[0] is BCD_CODE[0] at PIN_72
--operation mode is output

BCD_CODE[0] = OUTPUT(ACC[0]);


--BCD_CODE[1] is BCD_CODE[1] at PIN_79
--operation mode is output

BCD_CODE[1] = OUTPUT(ACC[1]);


--BCD_CODE[2] is BCD_CODE[2] at PIN_50
--operation mode is output

BCD_CODE[2] = OUTPUT(ACC[2]);


--BCD_CODE[3] is BCD_CODE[3] at PIN_17
--operation mode is output

BCD_CODE[3] = OUTPUT(ACC[3]);


--BCD_CODE[4] is BCD_CODE[4] at PIN_80
--operation mode is output

BCD_CODE[4] = OUTPUT(ACC[4]);


--BCD_CODE[5] is BCD_CODE[5] at PIN_47
--operation mode is output

BCD_CODE[5] = OUTPUT(ACC[5]);


--BCD_CODE[6] is BCD_CODE[6] at PIN_25
--operation mode is output

BCD_CODE[6] = OUTPUT(ACC[6]);


--BCD_CODE[7] is BCD_CODE[7] at PIN_18
--operation mode is output

BCD_CODE[7] = OUTPUT(ACC[7]);


--BCD_CODE[8] is BCD_CODE[8] at PIN_78
--operation mode is output

BCD_CODE[8] = OUTPUT(ACC[8]);


--BCD_CODE[9] is BCD_CODE[9] at PIN_19
--operation mode is output

BCD_CODE[9] = OUTPUT(ACC[9]);


--BCD_CODE[10] is BCD_CODE[10] at PIN_64
--operation mode is output

BCD_CODE[10] = OUTPUT(ACC[10]);


--BCD_CODE[11] is BCD_CODE[11] at PIN_48
--operation mode is output

BCD_CODE[11] = OUTPUT(ACC[11]);


--BCD_CODE[12] is BCD_CODE[12] at PIN_59
--operation mode is output

BCD_CODE[12] = OUTPUT(ACC[12]);


--BCD_CODE[13] is BCD_CODE[13] at PIN_69
--operation mode is output

BCD_CODE[13] = OUTPUT(ACC[13]);


--BCD_CODE[14] is BCD_CODE[14] at PIN_65
--operation mode is output

BCD_CODE[14] = OUTPUT(ACC[14]);


--BCD_CODE[15] is BCD_CODE[15] at PIN_49
--operation mode is output

BCD_CODE[15] = OUTPUT(ACC[15]);


--SELOUT[0] is SELOUT[0] at PIN_11
--operation mode is output

SELOUT[0] = OUTPUT(D1_q[4]);


--SELOUT[1] is SELOUT[1] at PIN_24
--operation mode is output

SELOUT[1] = OUTPUT(D1_q[5]);


--SEGOUT[0] is SEGOUT[0] at PIN_29
--operation mode is output

SEGOUT[0] = OUTPUT(A1L236);


--SEGOUT[1] is SEGOUT[1] at PIN_28
--operation mode is output

SEGOUT[1] = OUTPUT(A1L240);


--SEGOUT[2] is SEGOUT[2] at PIN_27
--operation mode is output

SEGOUT[2] = OUTPUT(A1L241);


--SEGOUT[3] is SEGOUT[3] at PIN_67
--operation mode is output

SEGOUT[3] = OUTPUT(A1L243);


--SEGOUT[4] is SEGOUT[4] at PIN_58
--operation mode is output

SEGOUT[4] = OUTPUT(A1L244);


--SEGOUT[5] is SEGOUT[5] at PIN_60
--operation mode is output

SEGOUT[5] = OUTPUT(A1L245);


--SEGOUT[6] is SEGOUT[6] at PIN_52
--operation mode is output

SEGOUT[6] = OUTPUT(A1L246);
上一頁 1 23
?? 文件大小 264 K
?? 上傳用戶 yyyz
?? 所屬分類 VHDL/FPGA/Verilog
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?? elec_lock.fit.eqn

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