?? fenpin.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FENPIN IS
PORT (
CLK : IN STD_LOGIC;
CLK_RD,CLK_WR : OUT STD_LOGIC; --AD1674控制信號
Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); --鎖存數(shù)據輸出
END FENPIN;
ARCHITECTURE behav OF FENPIN IS
Signal Q : STD_LOGIC_VECTOR(7 DOWNTO 0);
Signal S : STD_LOGIC_VECTOR(1 DOWNTO 0) ; --keyboard scan about 15Hz ***
SIGNAL SEL : STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk_4M) --各種時鐘產生
Begin
IF CLK_4M'Event AND CLK_4M = '1' then
Q <= Q+1;
END IF;
END PROCESS;
CLK <= Q(0) ; --CLK = CLK_DEBOUNCE
CLK_KEYBOARD <= Q(5 DOWNTO 4) ; -- ***00-01-10-11 ----- 32分頻
CLK_DISPLAY <= Q(5 DOWNTO 4) ;
END ARCHITECTURE BEHAV;
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